FPGA/verilog-axi
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-axi.git synced 2025-02-04 07:12:57 +08:00
Code Issues Projects Releases Wiki Activity
187 Commits 2 Branches 0 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Alex Forencich
2a7d190eb4 Update test durations 2021-06-03 13:48:33 -07:00
Alex Forencich
5d2389fd81 Add test durations for pytest-split 2020-12-04 15:41:35 -08:00