FPGA/verilog-axi
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3 Commits

Author SHA1 Message Date
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
21dbe318b4 Add AXI lite clock domain crossing module, testbench, and timing constraints 2019-07-09 00:18:27 -07:00