FPGA/verilog-axi
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5 Commits

Author SHA1 Message Date
Alex Forencich
38915fb533 Fix reset CDC in AXI VFIFO 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-30 00:12:13 -07:00
Alex Forencich
59d37ee850 Add AXI virtual FIFO 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-28 20:59:47 -07:00
Alex Forencich
f521fb6435 Update timing constraints to handle clocks from OOC IP that are not constrained during synthesis 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-17 13:40:36 -08:00
Alex Forencich
9c4012f58d Reorganize timing constraints 2021-05-20 15:15:51 -07:00
Alex Forencich
21dbe318b4 Add AXI lite clock domain crossing module, testbench, and timing constraints 2019-07-09 00:18:27 -07:00