FPGA/verilog-axi
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12 Commits

Author SHA1 Message Date
Alex Forencich
00c200f881 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-17 16:18:44 -08:00
Alex Forencich
e10a7ae88e Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 22:12:16 -08:00
Alex Forencich
293cfe153c Use start_soon instead of fork 2021-12-10 18:23:39 -08:00
Alex Forencich
fbb507be82 Remove deprecated assigments 2021-11-15 14:31:28 -08:00
Alex Forencich
ee9c719bf4 Add error reporting to DMA modules 2021-08-01 10:59:38 -07:00
Alex Forencich
a45c36e802 Update testbenches 2021-04-12 22:55:38 -07:00
Alex Forencich
be689ebb77 Update testbenches 2021-03-06 19:55:50 -08:00
Alex Forencich
03a78413c5 Rework sim_build output directory, fix default makefile target 2020-12-29 16:09:02 -08:00
Alex Forencich
db58c836f6 Use absolute path to test directory 2020-12-28 18:52:47 -08:00
Alex Forencich
9ab1fb44b1 Convert send/recv to blocking 2020-12-18 16:50:50 -08:00
Alex Forencich
ca7f0131ea Remove unnecessary __init__.py files 2020-12-15 18:59:49 -08:00
Alex Forencich
72f5a2d1cb Add cocotb testbenches 2020-12-04 15:32:14 -08:00