FPGA/verilog-axi
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2 Commits

Author SHA1 Message Date
Alex Forencich
61df54e62d Add M_REGIONS and M_SECURE parameters, add address range overlap check 2018-12-03 13:17:45 -08:00
Alex Forencich
e696abbdff Add AXI lite shared interconnect module and testbench 2018-08-22 20:34:31 -07:00