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Author SHA1 Message Date
Alex Forencich
0afd441eba Fix active operation count logic 2021-02-17 21:14:51 -08:00
Alex Forencich
e5f5b1c352 Remove unused regs 2021-02-17 18:30:55 -08:00
Alex Forencich
68387161d4 Track active operation count to prevent status FIFO overflow 2021-02-17 18:29:44 -08:00
Alex Forencich
83b5d30347 Rewrite resets 2021-02-17 18:06:47 -08:00
Alex Forencich
ac69ddfa22 Update github actions 2021-01-16 13:38:10 -08:00
Alex Forencich
03a78413c5 Rework sim_build output directory, fix default makefile target 2020-12-29 16:09:02 -08:00
Alex Forencich
3a59569105 Remove extraneous import 2020-12-28 18:53:00 -08:00
Alex Forencich
db58c836f6 Use absolute path to test directory 2020-12-28 18:52:47 -08:00
Alex Forencich
9ab1fb44b1 Convert send/recv to blocking 2020-12-18 16:50:50 -08:00
Alex Forencich
ca7f0131ea Remove unnecessary __init__.py files 2020-12-15 18:59:49 -08:00
Alex Forencich
be767f8ee7 Update readme 2020-12-04 16:18:28 -08:00
Alex Forencich
f8ff8a98d5 Remove README symlink 2020-12-04 16:15:32 -08:00
Alex Forencich
face7776d4 Add Github Actions regresion testing 2020-12-04 15:50:56 -08:00
Alex Forencich
bd4e574b36 Add posargs to tox.ini 2020-12-04 15:49:51 -08:00
Alex Forencich
5d2389fd81 Add test durations for pytest-split 2020-12-04 15:41:35 -08:00
Alex Forencich
de53699ed4 Add top-level makefile 2020-12-04 15:41:10 -08:00
Alex Forencich
72f5a2d1cb Add cocotb testbenches 2020-12-04 15:32:14 -08:00
Alex Forencich
8fb827a18b Add tox and pytest configuration 2020-12-04 15:30:48 -08:00
Alex Forencich
3d2364e19e Add wrapper generators 2020-12-04 15:21:14 -08:00
Alex Forencich
e4c4222fa9 Use wlast instead of awlen to detect end of write burst 2020-11-15 11:26:39 -08:00
Alex Forencich
c7d74b6425 Fix unaligned backpressure issue in AXI DMA write module 2020-11-14 20:12:24 -08:00
Alex Forencich
0eda0767af Rewrite 4K address boundary crossing checks 2020-11-11 22:29:40 -08:00
Alex Forencich
cd06f0b7dc Drop entire write operation on address decode fail in axi_interconnect 2020-10-19 00:13:40 -07:00
Alex Forencich
2c6185c0a5 Rewrite resets 2020-08-27 13:26:03 -07:00
Alex Forencich
00e2756385 Rewrite priority encoder to remove recusive construction 2020-08-17 18:28:59 -07:00
Alex Forencich
c1f31e537e Remove unnecessary wait state when output is ready 2020-08-17 00:13:02 -07:00
Alex Forencich
ba0b96ca34 Use logical operators 2020-08-17 00:11:52 -07:00
Alex Forencich
8b789c89ae Reset count_reg in axi_fifo_rd 2020-08-17 00:09:06 -07:00
Alex Forencich
9b03dfdb1a Fix backpressure bug 2020-04-12 23:33:15 -07:00
Alex Forencich
8ff77c8ae7 Fix reg name 2020-04-12 22:13:12 -07:00
Alex Forencich
82030d3720 Use correct RAM size for initialization 2019-11-24 15:38:10 -08:00
Alex Forencich
7c69ab9e49 Add default addressing capability to interconnect modules 2019-10-31 14:44:26 -07:00
Alex Forencich
7583ce3ea3 Print addressing configuration 2019-10-30 23:22:45 -07:00
Alex Forencich
ed6f5b3655 Update overlap error message 2019-10-30 23:21:29 -07:00
Alex Forencich
4e95fb3677 Bypass check when unneeded 2019-10-30 22:57:56 -07:00
Alex Forencich
25454e712e Remove constant regs 2019-10-30 22:56:27 -07:00
Alex Forencich
a4bc99bb1b Fix parameters 2019-09-05 05:23:20 -07:00
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
62cbaa1bd1 Remove extraneous code 2019-07-25 15:44:37 -07:00
Alex Forencich
8547057f32 Fix to enable M_COUNT of 1 2019-07-24 18:18:44 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
d694a67190 Update priority encoder 2019-07-24 14:22:47 -07:00
Alex Forencich
23a14dc5df Update readme 2019-07-09 00:18:58 -07:00
Alex Forencich
21dbe318b4 Add AXI lite clock domain crossing module, testbench, and timing constraints 2019-07-09 00:18:27 -07:00
Alex Forencich
36523dd7cc Fix typo 2019-07-08 17:57:47 -07:00
Alex Forencich
f924f75b70 Use computed word size 2019-07-08 17:57:30 -07:00
Alex Forencich
7591cb4d1c Update readme 2019-07-08 17:53:39 -07:00
Alex Forencich
ed344f352f Add AXI to AXI lite adapter modules and testbenches 2019-07-08 17:51:12 -07:00
Alex Forencich
f5830b6407 Backpressure updates 2019-07-08 17:34:09 -07:00
Alex Forencich
abcb20612e Remove redundant code 2019-07-08 00:28:27 -07:00