FPGA/verilog-axi
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8 Commits

Author SHA1 Message Date
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
83b5d30347 Rewrite resets 2021-02-17 18:06:47 -08:00
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
7b33dde069 Fix state encoding 2019-05-06 17:37:09 -07:00
Alex Forencich
685353c6e4 Rework AXI memory interfaces 2019-04-06 23:16:21 -07:00
Alex Forencich
e9cd97f0b4 Pass through more signals in AXI RAM interfaces 2019-02-26 01:25:03 -08:00
Alex Forencich
57dd292ae9 Add AXI RAM interface modules, AXI dual port RAM module, and testbench 2019-02-01 18:22:03 -08:00