FPGA/verilog-axi
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3 Commits

Author SHA1 Message Date
Alex Forencich
97cbbd1781 Don't crash when omitting read or write port connections 2018-08-16 12:50:14 -07:00
Alex Forencich
4adcf9c7d0 Add prot and resp signal encoding constants 2018-08-15 23:02:57 -07:00
Alex Forencich
57abfa66bc Add MyHDL AXI4 Lite master model, RAM model, and testbench 2018-08-14 23:49:11 -07:00