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Author SHA1 Message Date
Alex Forencich
302a23209f Add missing wires 2021-10-20 13:00:44 -07:00
Alex Forencich
a6a9a2ebd8 Update readme 2021-08-29 19:16:43 -07:00
Alex Forencich
5c2c6fd2bb Add AXI lite register interface modules 2021-08-29 19:09:52 -07:00
Alex Forencich
6b108481b8 Update interconnect address handling 2021-08-26 16:48:31 -07:00
Alex Forencich
fe283eee02 Update readme 2021-08-11 01:25:42 -07:00
Alex Forencich
26534e75ce Add AXI lite crossbar module and testbench 2021-08-11 01:23:14 -07:00
Alex Forencich
39dc8662b6 Remove duplicate code 2021-08-11 01:16:02 -07:00
Alex Forencich
bf3143a79f Fix test name 2021-08-03 01:54:00 -07:00
Alex Forencich
fceea6f8d8 Add output FIFOs to DMA engines 2021-08-03 01:53:18 -07:00
Alex Forencich
ee9c719bf4 Add error reporting to DMA modules 2021-08-01 10:59:38 -07:00
Alex Forencich
db826e489b Set algorithm for pytest-split 2021-08-01 01:19:07 -07:00
Alex Forencich
2a7d190eb4 Update test durations 2021-06-03 13:48:33 -07:00
Alex Forencich
5063aeadcd Remove string parameters 2021-06-02 17:04:53 -07:00
Alex Forencich
51caad0810 Extract port counts 2021-06-01 13:22:48 -07:00
Alex Forencich
a852697707 Fix instance names in wrappers 2021-06-01 13:18:11 -07:00
Alex Forencich
9c4012f58d Reorganize timing constraints 2021-05-20 15:15:51 -07:00
Alex Forencich
314ea7dbf9 Update readme 2021-04-12 22:55:49 -07:00
Alex Forencich
a45c36e802 Update testbenches 2021-04-12 22:55:38 -07:00
Alex Forencich
bf2a779e48 Rewrite test 2021-03-24 22:00:20 -07:00
Alex Forencich
bb30f0a50f Extract parameter values from cocotb.top 2021-03-22 18:07:04 -07:00
Alex Forencich
1f3920afcc Use release version of cocotb for CI 2021-03-17 19:10:04 -07:00
Alex Forencich
be689ebb77 Update testbenches 2021-03-06 19:55:50 -08:00
Alex Forencich
0afd441eba Fix active operation count logic 2021-02-17 21:14:51 -08:00
Alex Forencich
e5f5b1c352 Remove unused regs 2021-02-17 18:30:55 -08:00
Alex Forencich
68387161d4 Track active operation count to prevent status FIFO overflow 2021-02-17 18:29:44 -08:00
Alex Forencich
83b5d30347 Rewrite resets 2021-02-17 18:06:47 -08:00
Alex Forencich
ac69ddfa22 Update github actions 2021-01-16 13:38:10 -08:00
Alex Forencich
03a78413c5 Rework sim_build output directory, fix default makefile target 2020-12-29 16:09:02 -08:00
Alex Forencich
3a59569105 Remove extraneous import 2020-12-28 18:53:00 -08:00
Alex Forencich
db58c836f6 Use absolute path to test directory 2020-12-28 18:52:47 -08:00
Alex Forencich
9ab1fb44b1 Convert send/recv to blocking 2020-12-18 16:50:50 -08:00
Alex Forencich
ca7f0131ea Remove unnecessary __init__.py files 2020-12-15 18:59:49 -08:00
Alex Forencich
be767f8ee7 Update readme 2020-12-04 16:18:28 -08:00
Alex Forencich
f8ff8a98d5 Remove README symlink 2020-12-04 16:15:32 -08:00
Alex Forencich
face7776d4 Add Github Actions regresion testing 2020-12-04 15:50:56 -08:00
Alex Forencich
bd4e574b36 Add posargs to tox.ini 2020-12-04 15:49:51 -08:00
Alex Forencich
5d2389fd81 Add test durations for pytest-split 2020-12-04 15:41:35 -08:00
Alex Forencich
de53699ed4 Add top-level makefile 2020-12-04 15:41:10 -08:00
Alex Forencich
72f5a2d1cb Add cocotb testbenches 2020-12-04 15:32:14 -08:00
Alex Forencich
8fb827a18b Add tox and pytest configuration 2020-12-04 15:30:48 -08:00
Alex Forencich
3d2364e19e Add wrapper generators 2020-12-04 15:21:14 -08:00
Alex Forencich
e4c4222fa9 Use wlast instead of awlen to detect end of write burst 2020-11-15 11:26:39 -08:00
Alex Forencich
c7d74b6425 Fix unaligned backpressure issue in AXI DMA write module 2020-11-14 20:12:24 -08:00
Alex Forencich
0eda0767af Rewrite 4K address boundary crossing checks 2020-11-11 22:29:40 -08:00
Alex Forencich
cd06f0b7dc Drop entire write operation on address decode fail in axi_interconnect 2020-10-19 00:13:40 -07:00
Alex Forencich
2c6185c0a5 Rewrite resets 2020-08-27 13:26:03 -07:00
Alex Forencich
00e2756385 Rewrite priority encoder to remove recusive construction 2020-08-17 18:28:59 -07:00
Alex Forencich
c1f31e537e Remove unnecessary wait state when output is ready 2020-08-17 00:13:02 -07:00
Alex Forencich
ba0b96ca34 Use logical operators 2020-08-17 00:11:52 -07:00
Alex Forencich
8b789c89ae Reset count_reg in axi_fifo_rd 2020-08-17 00:09:06 -07:00