FPGA/verilog-axi
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-axi.git synced 2025-01-14 06:42:55 +08:00
Code Issues Projects Releases Wiki Activity
165 Commits 2 Branches 0 Tags
Commit Graph

110 Commits

Author SHA1 Message Date
Alex Forencich
b15e8d9f63 Add AXI adapters and testbenchs 2018-08-20 19:10:08 -07:00
Alex Forencich
e06d607b85 Add AXI lite width adapter and testbenches 2018-08-16 16:37:11 -07:00
Alex Forencich
48577f3a2d Add simple register as a per-channel option to AXI register modules 2018-08-16 13:25:07 -07:00
Alex Forencich
d541c64bc0 Add AXI lite registers and testbenches 2018-08-16 13:01:45 -07:00
Alex Forencich
ad453b12db Add AXI lite RAM module and testbench 2018-08-14 23:49:40 -07:00
Alex Forencich
2113bb1795 Add AXI registers and testbenches 2018-08-13 23:36:47 -07:00
Alex Forencich
5f302d8106 Fix some more issues in AXI RAM module 2018-08-13 16:00:29 -07:00
Alex Forencich
66b20c171b Add AXI FIFOs and testbenches 2018-08-13 15:31:04 -07:00
Alex Forencich
0cb456e047 Improve testbench and fix bugs in axi_ram 2018-08-11 22:32:05 -07:00
Alex Forencich
f4cca52660 Initial commit 2018-07-29 19:04:30 -07:00