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Author SHA1 Message Date
Alex Forencich
04dd6a34d7 Fix combinatorial loop 2019-02-20 18:48:27 -08:00
Alex Forencich
7654d874ae Fix out of range access due to off by one error 2019-02-11 19:30:57 -08:00
Alex Forencich
57dd292ae9 Add AXI RAM interface modules, AXI dual port RAM module, and testbench 2019-02-01 18:22:03 -08:00
Alex Forencich
199a5544ca Use correct wait 2019-02-01 17:28:22 -08:00
Alex Forencich
787f198970 Add AXI lite dual-port RAM module and testbench 2019-01-17 17:48:23 -08:00
Alex Forencich
b1f40411ad Remove unnecessary reset 2019-01-17 17:09:55 -08:00
Alex Forencich
818fac5daa Update signal names 2019-01-16 19:37:15 -08:00
Alex Forencich
523bf689d8 Add optional output pipeline register to AXI lite RAM 2019-01-09 00:25:40 -08:00
Alex Forencich
513a53e52d Add AXI DMA module and testbench 2018-12-27 14:21:06 -08:00
Alex Forencich
41f8667310 Add AXI write DMA module and testbenches 2018-12-27 14:15:51 -08:00
Alex Forencich
21ed77e4c0 Add AXI stream endpoint module 2018-12-27 13:49:48 -08:00
Alex Forencich
50eb71221b Change cycle to segment, clean up parameters 2018-12-06 18:32:46 -08:00
Alex Forencich
76fba3ac84 Add AXI central DMA module and testbenches 2018-12-06 17:27:44 -08:00
Alex Forencich
275cb09205 Minor reorganization 2018-12-06 17:19:30 -08:00
Alex Forencich
3587cf5285 Fix AXI memory model bug 2018-12-06 15:14:54 -08:00
Alex Forencich
e5e2aa8867 Use correct parameter 2018-12-06 01:21:42 -08:00
Alex Forencich
e7b6f43c8c Fix multi-driven net issue 2018-12-04 21:03:39 -08:00
Alex Forencich
7d0f3ef7a1 Fix address range overlap check to support arbitrary address widths 2018-12-04 17:00:26 -08:00
Alex Forencich
43234018cd Add AXI read DMA module and testbenches 2018-12-03 23:29:22 -08:00
Alex Forencich
61df54e62d Add M_REGIONS and M_SECURE parameters, add address range overlap check 2018-12-03 13:17:45 -08:00
Alex Forencich
7141a75ce8 Remove region inputs 2018-12-03 13:15:55 -08:00
Alex Forencich
b54d3eb866 Change cycle to segment, clean up parameters 2018-12-03 12:52:00 -08:00
Alex Forencich
0dbf0b1cff Add optional output pipeline register to AXI RAM module 2018-11-27 01:17:31 -08:00
Alex Forencich
b289e02fe4 Remove extraneous code 2018-08-26 14:06:57 -07:00
Alex Forencich
71427e7cf0 Update default parameters 2018-08-26 14:05:10 -07:00
Alex Forencich
07a4da3bea Fix connect logic 2018-08-23 16:20:58 -07:00
Alex Forencich
4f01dfb7d5 Support single slave interface 2018-08-23 14:43:57 -07:00
Alex Forencich
f1fb5b368c Fix connect logic 2018-08-23 14:41:40 -07:00
Alex Forencich
a25c4b17eb Add AXI shared interconnect and testbench 2018-08-22 23:42:31 -07:00
Alex Forencich
1753a2e6cf Remove extraneous logic 2018-08-22 22:28:15 -07:00
Alex Forencich
8427aa12bf Simplify request logic 2018-08-22 22:27:52 -07:00
Alex Forencich
fe7396a31e Update readme 2018-08-22 21:55:08 -07:00
Alex Forencich
0e36f647cb Add arbiter and priority encoder modules 2018-08-22 21:50:31 -07:00
Alex Forencich
82a13479e7 Add decode error tests 2018-08-22 20:43:28 -07:00
Alex Forencich
e696abbdff Add AXI lite shared interconnect module and testbench 2018-08-22 20:34:31 -07:00
Alex Forencich
2a4c63e859 Change default address width to 32 2018-08-21 22:38:32 -07:00
Alex Forencich
7c40254d7e Remove redundant testbenches 2018-08-21 22:27:47 -07:00
Alex Forencich
6a002e2ce0 Add CONVERT_NARROW_BURST and FORWARD_ID parameters to AXI adapter 2018-08-20 23:23:00 -07:00
Alex Forencich
b15e8d9f63 Add AXI adapters and testbenchs 2018-08-20 19:10:08 -07:00
Alex Forencich
160f20bc8c Change default awcache/arcache value 2018-08-17 16:29:12 -07:00
Alex Forencich
e06d607b85 Add AXI lite width adapter and testbenches 2018-08-16 16:37:11 -07:00
Alex Forencich
48577f3a2d Add simple register as a per-channel option to AXI register modules 2018-08-16 13:25:07 -07:00
Alex Forencich
d541c64bc0 Add AXI lite registers and testbenches 2018-08-16 13:01:45 -07:00
Alex Forencich
97cbbd1781 Don't crash when omitting read or write port connections 2018-08-16 12:50:14 -07:00
Alex Forencich
4adcf9c7d0 Add prot and resp signal encoding constants 2018-08-15 23:02:57 -07:00
Alex Forencich
ad453b12db Add AXI lite RAM module and testbench 2018-08-14 23:49:40 -07:00
Alex Forencich
57abfa66bc Add MyHDL AXI4 Lite master model, RAM model, and testbench 2018-08-14 23:49:11 -07:00
Alex Forencich
b8e6b30717 Don't use narrow bursts for setup and checking in AXI RAM testbench 2018-08-14 23:44:15 -07:00
Alex Forencich
5614f7dafe When pausing the AXI model, do not drop valid signals if they are asserted and waiting for a ready signal assert 2018-08-14 23:38:08 -07:00
Alex Forencich
09759518fc ID always zero if ID pins not connected 2018-08-14 21:48:24 -07:00