FPGA/verilog-axi
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5 Commits

Author SHA1 Message Date
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
50eb71221b Change cycle to segment, clean up parameters 2018-12-06 18:32:46 -08:00
Alex Forencich
2a4c63e859 Change default address width to 32 2018-08-21 22:38:32 -07:00
Alex Forencich
e06d607b85 Add AXI lite width adapter and testbenches 2018-08-16 16:37:11 -07:00