FPGA/verilog-axi
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8 Commits

Author SHA1 Message Date
Alex Forencich
9b03dfdb1a Fix backpressure bug 2020-04-12 23:33:15 -07:00
Alex Forencich
8ff77c8ae7 Fix reg name 2020-04-12 22:13:12 -07:00
Alex Forencich
82030d3720 Use correct RAM size for initialization 2019-11-24 15:38:10 -08:00
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
f924f75b70 Use computed word size 2019-07-08 17:57:30 -07:00
Alex Forencich
e9cd97f0b4 Pass through more signals in AXI RAM interfaces 2019-02-26 01:25:03 -08:00
Alex Forencich
57dd292ae9 Add AXI RAM interface modules, AXI dual port RAM module, and testbench 2019-02-01 18:22:03 -08:00