FPGA/verilog-axi
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6 Commits

Author SHA1 Message Date
Alex Forencich
664949b7d6 Cleanup 2019-04-12 12:39:35 -07:00
Alex Forencich
685353c6e4 Rework AXI memory interfaces 2019-04-06 23:16:21 -07:00
Alex Forencich
0dbf0b1cff Add optional output pipeline register to AXI RAM module 2018-11-27 01:17:31 -08:00
Alex Forencich
5f302d8106 Fix some more issues in AXI RAM module 2018-08-13 16:00:29 -07:00
Alex Forencich
0cb456e047 Improve testbench and fix bugs in axi_ram 2018-08-11 22:32:05 -07:00
Alex Forencich
f4cca52660 Initial commit 2018-07-29 19:04:30 -07:00