FPGA/verilog-axi
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4 Commits

Author SHA1 Message Date
Alex Forencich
b8e6b30717 Don't use narrow bursts for setup and checking in AXI RAM testbench 2018-08-14 23:44:15 -07:00
Alex Forencich
5f302d8106 Fix some more issues in AXI RAM module 2018-08-13 16:00:29 -07:00
Alex Forencich
0cb456e047 Improve testbench and fix bugs in axi_ram 2018-08-11 22:32:05 -07:00
Alex Forencich
f4cca52660 Initial commit 2018-07-29 19:04:30 -07:00