FPGA/verilog-axi
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-axi.git synced 2025-01-28 07:02:56 +08:00
Code Issues Projects Releases Wiki Activity
41 Commits 2 Branches 0 Tags
Commit Graph

7 Commits

Author SHA1 Message Date
Alex Forencich
71427e7cf0 Update default parameters 2018-08-26 14:05:10 -07:00
Alex Forencich
07a4da3bea Fix connect logic 2018-08-23 16:20:58 -07:00
Alex Forencich
4f01dfb7d5 Support single slave interface 2018-08-23 14:43:57 -07:00
Alex Forencich
f1fb5b368c Fix connect logic 2018-08-23 14:41:40 -07:00
Alex Forencich
1753a2e6cf Remove extraneous logic 2018-08-22 22:28:15 -07:00
Alex Forencich
8427aa12bf Simplify request logic 2018-08-22 22:27:52 -07:00
Alex Forencich
e696abbdff Add AXI lite shared interconnect module and testbench 2018-08-22 20:34:31 -07:00