FPGA/verilog-axi
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179 Commits 2 Branches 0 Tags
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14 Commits

Author SHA1 Message Date
Alex Forencich
0b16849b57 Add attributes to RAMs for proper synthesis in Quartus 2021-11-04 20:43:13 -07:00
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
fceea6f8d8 Add output FIFOs to DMA engines 2021-08-03 01:53:18 -07:00
Alex Forencich
ee9c719bf4 Add error reporting to DMA modules 2021-08-01 10:59:38 -07:00
Alex Forencich
83b5d30347 Rewrite resets 2021-02-17 18:06:47 -08:00
Alex Forencich
0eda0767af Rewrite 4K address boundary crossing checks 2020-11-11 22:29:40 -08:00
Alex Forencich
4e95fb3677 Bypass check when unneeded 2019-10-30 22:57:56 -07:00
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
94a3be6e1d Fix possible backpressure issue 2019-06-22 12:47:52 -07:00
Alex Forencich
275cb09205 Minor reorganization 2018-12-06 17:19:30 -08:00
Alex Forencich
e5e2aa8867 Use correct parameter 2018-12-06 01:21:42 -08:00
Alex Forencich
e7b6f43c8c Fix multi-driven net issue 2018-12-04 21:03:39 -08:00
Alex Forencich
43234018cd Add AXI read DMA module and testbenches 2018-12-03 23:29:22 -08:00