FPGA/verilog-axi
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179 Commits 2 Branches 0 Tags
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9 Commits

Author SHA1 Message Date
Alex Forencich
0b16849b57 Add attributes to RAMs for proper synthesis in Quartus 2021-11-04 20:43:13 -07:00
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
2c6185c0a5 Rewrite resets 2020-08-27 13:26:03 -07:00
Alex Forencich
c1f31e537e Remove unnecessary wait state when output is ready 2020-08-17 00:13:02 -07:00
Alex Forencich
ba0b96ca34 Use logical operators 2020-08-17 00:11:52 -07:00
Alex Forencich
8b789c89ae Reset count_reg in axi_fifo_rd 2020-08-17 00:09:06 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
2a4c63e859 Change default address width to 32 2018-08-21 22:38:32 -07:00
Alex Forencich
66b20c171b Add AXI FIFOs and testbenches 2018-08-13 15:31:04 -07:00