FPGA/verilog-axi
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4 Commits

Author SHA1 Message Date
Alex Forencich
8b789c89ae Reset count_reg in axi_fifo_rd 2020-08-17 00:09:06 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
2a4c63e859 Change default address width to 32 2018-08-21 22:38:32 -07:00
Alex Forencich
66b20c171b Add AXI FIFOs and testbenches 2018-08-13 15:31:04 -07:00