FPGA/verilog-axi
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-axi.git synced 2025-02-04 07:12:57 +08:00
Code Issues Projects Releases Wiki Activity
107 Commits 2 Branches 0 Tags
Commit Graph

7 Commits

Author SHA1 Message Date
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
8547057f32 Fix to enable M_COUNT of 1 2019-07-24 18:18:44 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
101be9fa2c Fix use before define 2019-03-12 13:15:11 -07:00
Alex Forencich
620526d581 Also match transfers by region 2019-03-12 12:58:56 -07:00
Alex Forencich
4d628c9171 Fix thread matching 2019-03-06 13:40:29 -08:00
Alex Forencich
7b713199ad Add AXI nonblocking crossbar interconnect module and testbench 2019-02-25 18:37:46 -08:00