FPGA/verilog-axi
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5 Commits

Author SHA1 Message Date
Alex Forencich
a4bc99bb1b Fix parameters 2019-09-05 05:23:20 -07:00
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
724f18113c Fix bug 2019-03-05 22:20:44 -08:00
Alex Forencich
7b713199ad Add AXI nonblocking crossbar interconnect module and testbench 2019-02-25 18:37:46 -08:00