FPGA/verilog-axi
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4 Commits

Author SHA1 Message Date
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
f924f75b70 Use computed word size 2019-07-08 17:57:30 -07:00
Alex Forencich
5581a76c0b Use correct clocks 2019-05-14 18:57:01 -07:00
Alex Forencich
787f198970 Add AXI lite dual-port RAM module and testbench 2019-01-17 17:48:23 -08:00