FPGA/verilog-axi
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42 Commits 2 Branches 0 Tags
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6 Commits

Author SHA1 Message Date
Alex Forencich
b289e02fe4 Remove extraneous code 2018-08-26 14:06:57 -07:00
Alex Forencich
71427e7cf0 Update default parameters 2018-08-26 14:05:10 -07:00
Alex Forencich
07a4da3bea Fix connect logic 2018-08-23 16:20:58 -07:00
Alex Forencich
4f01dfb7d5 Support single slave interface 2018-08-23 14:43:57 -07:00
Alex Forencich
f1fb5b368c Fix connect logic 2018-08-23 14:41:40 -07:00
Alex Forencich
a25c4b17eb Add AXI shared interconnect and testbench 2018-08-22 23:42:31 -07:00