FPGA/verilog-axi
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-axi.git synced 2025-01-14 06:42:55 +08:00
Code Issues Projects Releases Wiki Activity
168 Commits 2 Branches 0 Tags
Commit Graph

113 Commits

Author SHA1 Message Date
Alex Forencich
b4bdfb6542 Add FIFO output register in AXI lite crossbar modules 2021-11-06 15:20:19 -07:00
Alex Forencich
0b16849b57 Add attributes to RAMs for proper synthesis in Quartus 2021-11-04 20:43:13 -07:00
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
302a23209f Add missing wires 2021-10-20 13:00:44 -07:00
Alex Forencich
5c2c6fd2bb Add AXI lite register interface modules 2021-08-29 19:09:52 -07:00
Alex Forencich
6b108481b8 Update interconnect address handling 2021-08-26 16:48:31 -07:00
Alex Forencich
26534e75ce Add AXI lite crossbar module and testbench 2021-08-11 01:23:14 -07:00
Alex Forencich
39dc8662b6 Remove duplicate code 2021-08-11 01:16:02 -07:00
Alex Forencich
fceea6f8d8 Add output FIFOs to DMA engines 2021-08-03 01:53:18 -07:00
Alex Forencich
ee9c719bf4 Add error reporting to DMA modules 2021-08-01 10:59:38 -07:00
Alex Forencich
5063aeadcd Remove string parameters 2021-06-02 17:04:53 -07:00
Alex Forencich
a852697707 Fix instance names in wrappers 2021-06-01 13:18:11 -07:00
Alex Forencich
0afd441eba Fix active operation count logic 2021-02-17 21:14:51 -08:00
Alex Forencich
e5f5b1c352 Remove unused regs 2021-02-17 18:30:55 -08:00
Alex Forencich
68387161d4 Track active operation count to prevent status FIFO overflow 2021-02-17 18:29:44 -08:00
Alex Forencich
83b5d30347 Rewrite resets 2021-02-17 18:06:47 -08:00
Alex Forencich
3d2364e19e Add wrapper generators 2020-12-04 15:21:14 -08:00
Alex Forencich
e4c4222fa9 Use wlast instead of awlen to detect end of write burst 2020-11-15 11:26:39 -08:00
Alex Forencich
c7d74b6425 Fix unaligned backpressure issue in AXI DMA write module 2020-11-14 20:12:24 -08:00
Alex Forencich
0eda0767af Rewrite 4K address boundary crossing checks 2020-11-11 22:29:40 -08:00
Alex Forencich
cd06f0b7dc Drop entire write operation on address decode fail in axi_interconnect 2020-10-19 00:13:40 -07:00
Alex Forencich
2c6185c0a5 Rewrite resets 2020-08-27 13:26:03 -07:00
Alex Forencich
00e2756385 Rewrite priority encoder to remove recusive construction 2020-08-17 18:28:59 -07:00
Alex Forencich
c1f31e537e Remove unnecessary wait state when output is ready 2020-08-17 00:13:02 -07:00
Alex Forencich
ba0b96ca34 Use logical operators 2020-08-17 00:11:52 -07:00
Alex Forencich
8b789c89ae Reset count_reg in axi_fifo_rd 2020-08-17 00:09:06 -07:00
Alex Forencich
9b03dfdb1a Fix backpressure bug 2020-04-12 23:33:15 -07:00
Alex Forencich
8ff77c8ae7 Fix reg name 2020-04-12 22:13:12 -07:00
Alex Forencich
82030d3720 Use correct RAM size for initialization 2019-11-24 15:38:10 -08:00
Alex Forencich
7c69ab9e49 Add default addressing capability to interconnect modules 2019-10-31 14:44:26 -07:00
Alex Forencich
7583ce3ea3 Print addressing configuration 2019-10-30 23:22:45 -07:00
Alex Forencich
ed6f5b3655 Update overlap error message 2019-10-30 23:21:29 -07:00
Alex Forencich
4e95fb3677 Bypass check when unneeded 2019-10-30 22:57:56 -07:00
Alex Forencich
25454e712e Remove constant regs 2019-10-30 22:56:27 -07:00
Alex Forencich
a4bc99bb1b Fix parameters 2019-09-05 05:23:20 -07:00
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
62cbaa1bd1 Remove extraneous code 2019-07-25 15:44:37 -07:00
Alex Forencich
8547057f32 Fix to enable M_COUNT of 1 2019-07-24 18:18:44 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
d694a67190 Update priority encoder 2019-07-24 14:22:47 -07:00
Alex Forencich
21dbe318b4 Add AXI lite clock domain crossing module, testbench, and timing constraints 2019-07-09 00:18:27 -07:00
Alex Forencich
f924f75b70 Use computed word size 2019-07-08 17:57:30 -07:00
Alex Forencich
ed344f352f Add AXI to AXI lite adapter modules and testbenches 2019-07-08 17:51:12 -07:00
Alex Forencich
f5830b6407 Backpressure updates 2019-07-08 17:34:09 -07:00
Alex Forencich
abcb20612e Remove redundant code 2019-07-08 00:28:27 -07:00
Alex Forencich
1bd22f5208 Ensure rready clear when returning to idle 2019-07-05 23:29:39 -07:00
Alex Forencich
3f21db4584 bresp handling update 2019-07-04 14:23:37 -07:00
Alex Forencich
7fd0f79f81 Remove extraneous parameter 2019-06-26 12:26:55 -07:00
Alex Forencich
94a3be6e1d Fix possible backpressure issue 2019-06-22 12:47:52 -07:00
Alex Forencich
f6acefbf94 Simplify logic 2019-06-22 01:51:06 -07:00