FPGA/verilog-axi
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5 Commits

Author SHA1 Message Date
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
83b5d30347 Rewrite resets 2021-02-17 18:06:47 -08:00
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
ed344f352f Add AXI to AXI lite adapter modules and testbenches 2019-07-08 17:51:12 -07:00