FPGA/verilog-axi
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168 Commits 2 Branches 0 Tags
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12 Commits

Author SHA1 Message Date
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
83b5d30347 Rewrite resets 2021-02-17 18:06:47 -08:00
Alex Forencich
82030d3720 Use correct RAM size for initialization 2019-11-24 15:38:10 -08:00
Alex Forencich
521c6d909e Include instance names in error messages 2019-07-25 16:33:27 -07:00
Alex Forencich
62dbc043e2 Add parameter documentation 2019-07-24 17:49:48 -07:00
Alex Forencich
f924f75b70 Use computed word size 2019-07-08 17:57:30 -07:00
Alex Forencich
664949b7d6 Cleanup 2019-04-12 12:39:35 -07:00
Alex Forencich
685353c6e4 Rework AXI memory interfaces 2019-04-06 23:16:21 -07:00
Alex Forencich
0dbf0b1cff Add optional output pipeline register to AXI RAM module 2018-11-27 01:17:31 -08:00
Alex Forencich
5f302d8106 Fix some more issues in AXI RAM module 2018-08-13 16:00:29 -07:00
Alex Forencich
0cb456e047 Improve testbench and fix bugs in axi_ram 2018-08-11 22:32:05 -07:00
Alex Forencich
f4cca52660 Initial commit 2018-07-29 19:04:30 -07:00