FPGA/verilog-axi
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3 Commits

Author SHA1 Message Date
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
6b108481b8 Update interconnect address handling 2021-08-26 16:48:31 -07:00
Alex Forencich
26534e75ce Add AXI lite crossbar module and testbench 2021-08-11 01:23:14 -07:00