FPGA/verilog-axi
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4 Commits

Author SHA1 Message Date
Alex Forencich
b4bdfb6542 Add FIFO output register in AXI lite crossbar modules 2021-11-06 15:20:19 -07:00
Alex Forencich
0b16849b57 Add attributes to RAMs for proper synthesis in Quartus 2021-11-04 20:43:13 -07:00
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
26534e75ce Add AXI lite crossbar module and testbench 2021-08-11 01:23:14 -07:00