FPGA/verilog-axi
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5 Commits

Author SHA1 Message Date
Alex Forencich
be689ebb77 Update testbenches 2021-03-06 19:55:50 -08:00
Alex Forencich
03a78413c5 Rework sim_build output directory, fix default makefile target 2020-12-29 16:09:02 -08:00
Alex Forencich
db58c836f6 Use absolute path to test directory 2020-12-28 18:52:47 -08:00
Alex Forencich
9ab1fb44b1 Convert send/recv to blocking 2020-12-18 16:50:50 -08:00
Alex Forencich
72f5a2d1cb Add cocotb testbenches 2020-12-04 15:32:14 -08:00