Alex Forencich
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cd06f0b7dc
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Drop entire write operation on address decode fail in axi_interconnect
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2020-10-19 00:13:40 -07:00 |
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Alex Forencich
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2c6185c0a5
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Rewrite resets
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2020-08-27 13:26:03 -07:00 |
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Alex Forencich
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00e2756385
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Rewrite priority encoder to remove recusive construction
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2020-08-17 18:28:59 -07:00 |
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Alex Forencich
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c1f31e537e
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Remove unnecessary wait state when output is ready
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2020-08-17 00:13:02 -07:00 |
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Alex Forencich
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ba0b96ca34
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Use logical operators
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2020-08-17 00:11:52 -07:00 |
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Alex Forencich
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8b789c89ae
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Reset count_reg in axi_fifo_rd
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2020-08-17 00:09:06 -07:00 |
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Alex Forencich
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9b03dfdb1a
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Fix backpressure bug
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2020-04-12 23:33:15 -07:00 |
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Alex Forencich
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8ff77c8ae7
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Fix reg name
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2020-04-12 22:13:12 -07:00 |
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Alex Forencich
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82030d3720
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Use correct RAM size for initialization
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2019-11-24 15:38:10 -08:00 |
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Alex Forencich
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7c69ab9e49
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Add default addressing capability to interconnect modules
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2019-10-31 14:44:26 -07:00 |
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Alex Forencich
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7583ce3ea3
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Print addressing configuration
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2019-10-30 23:22:45 -07:00 |
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Alex Forencich
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ed6f5b3655
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Update overlap error message
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2019-10-30 23:21:29 -07:00 |
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Alex Forencich
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4e95fb3677
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Bypass check when unneeded
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2019-10-30 22:57:56 -07:00 |
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Alex Forencich
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25454e712e
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Remove constant regs
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2019-10-30 22:56:27 -07:00 |
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Alex Forencich
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a4bc99bb1b
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Fix parameters
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2019-09-05 05:23:20 -07:00 |
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Alex Forencich
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521c6d909e
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Include instance names in error messages
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2019-07-25 16:33:27 -07:00 |
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Alex Forencich
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62cbaa1bd1
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Remove extraneous code
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2019-07-25 15:44:37 -07:00 |
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Alex Forencich
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8547057f32
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Fix to enable M_COUNT of 1
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2019-07-24 18:18:44 -07:00 |
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Alex Forencich
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62dbc043e2
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Add parameter documentation
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2019-07-24 17:49:48 -07:00 |
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Alex Forencich
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d694a67190
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Update priority encoder
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2019-07-24 14:22:47 -07:00 |
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Alex Forencich
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23a14dc5df
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Update readme
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2019-07-09 00:18:58 -07:00 |
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Alex Forencich
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21dbe318b4
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Add AXI lite clock domain crossing module, testbench, and timing constraints
|
2019-07-09 00:18:27 -07:00 |
|
Alex Forencich
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36523dd7cc
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Fix typo
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2019-07-08 17:57:47 -07:00 |
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Alex Forencich
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f924f75b70
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Use computed word size
|
2019-07-08 17:57:30 -07:00 |
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Alex Forencich
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7591cb4d1c
|
Update readme
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2019-07-08 17:53:39 -07:00 |
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Alex Forencich
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ed344f352f
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Add AXI to AXI lite adapter modules and testbenches
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2019-07-08 17:51:12 -07:00 |
|
Alex Forencich
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f5830b6407
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Backpressure updates
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2019-07-08 17:34:09 -07:00 |
|
Alex Forencich
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abcb20612e
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Remove redundant code
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2019-07-08 00:28:27 -07:00 |
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Alex Forencich
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1bd22f5208
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Ensure rready clear when returning to idle
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2019-07-05 23:29:39 -07:00 |
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Alex Forencich
|
3f21db4584
|
bresp handling update
|
2019-07-04 14:23:37 -07:00 |
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Alex Forencich
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7fd0f79f81
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Remove extraneous parameter
|
2019-06-26 12:26:55 -07:00 |
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Alex Forencich
|
94a3be6e1d
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Fix possible backpressure issue
|
2019-06-22 12:47:52 -07:00 |
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Alex Forencich
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f6acefbf94
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Simplify logic
|
2019-06-22 01:51:06 -07:00 |
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Alex Forencich
|
ebbaea908b
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Add strb_offset_mask_reg
|
2019-06-22 00:13:11 -07:00 |
|
Alex Forencich
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b1edaf1ae4
|
Optimize check
|
2019-06-22 00:05:15 -07:00 |
|
Alex Forencich
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6ed937d521
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Add zero offset reg
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2019-06-21 20:42:20 -07:00 |
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Alex Forencich
|
967aa8c2f3
|
Mask instead of barrel shift
|
2019-06-21 20:38:09 -07:00 |
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Alex Forencich
|
435f0b8749
|
Timing optimization of wstrb
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2019-06-21 12:04:58 -07:00 |
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Alex Forencich
|
834d6a4b2d
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Improve timing for unaligned operations (shift_axis_extra_cycle)
|
2019-06-15 21:27:41 -07:00 |
|
Alex Forencich
|
b0cda50aba
|
Fix AXIL interconnect read bug
|
2019-06-12 17:57:39 -07:00 |
|
Alex Forencich
|
5581a76c0b
|
Use correct clocks
|
2019-05-14 18:57:01 -07:00 |
|
Alex Forencich
|
7b33dde069
|
Fix state encoding
|
2019-05-06 17:37:09 -07:00 |
|
Alex Forencich
|
664949b7d6
|
Cleanup
|
2019-04-12 12:39:35 -07:00 |
|
Alex Forencich
|
685353c6e4
|
Rework AXI memory interfaces
|
2019-04-06 23:16:21 -07:00 |
|
Alex Forencich
|
a60e1f726f
|
Fix use before define
|
2019-03-18 14:02:10 -07:00 |
|
Alex Forencich
|
f128190130
|
Ensure transfer is terminated at the end of the input frame
|
2019-03-13 14:48:05 -07:00 |
|
Alex Forencich
|
101be9fa2c
|
Fix use before define
|
2019-03-12 13:15:11 -07:00 |
|
Alex Forencich
|
620526d581
|
Also match transfers by region
|
2019-03-12 12:58:56 -07:00 |
|
Alex Forencich
|
e71a62e6a1
|
Fix backpressure issue
|
2019-03-07 17:45:25 -08:00 |
|
Alex Forencich
|
4d628c9171
|
Fix thread matching
|
2019-03-06 13:40:29 -08:00 |
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