FPGA/verilog-axi
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102 Commits 2 Branches 0 Tags
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7 Commits

Author SHA1 Message Date
Alex Forencich
f5830b6407 Backpressure updates 2019-07-08 17:34:09 -07:00
Alex Forencich
abcb20612e Remove redundant code 2019-07-08 00:28:27 -07:00
Alex Forencich
1bd22f5208 Ensure rready clear when returning to idle 2019-07-05 23:29:39 -07:00
Alex Forencich
b54d3eb866 Change cycle to segment, clean up parameters 2018-12-03 12:52:00 -08:00
Alex Forencich
2a4c63e859 Change default address width to 32 2018-08-21 22:38:32 -07:00
Alex Forencich
6a002e2ce0 Add CONVERT_NARROW_BURST and FORWARD_ID parameters to AXI adapter 2018-08-20 23:23:00 -07:00
Alex Forencich
b15e8d9f63 Add AXI adapters and testbenchs 2018-08-20 19:10:08 -07:00