FPGA/verilog-axi
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-axi.git synced 2025-01-14 06:42:55 +08:00
Code Issues Projects Releases Wiki Activity
102 Commits 2 Branches 0 Tags
Commit Graph

3 Commits

Author SHA1 Message Date
Alex Forencich
50eb71221b Change cycle to segment, clean up parameters 2018-12-06 18:32:46 -08:00
Alex Forencich
2a4c63e859 Change default address width to 32 2018-08-21 22:38:32 -07:00
Alex Forencich
e06d607b85 Add AXI lite width adapter and testbenches 2018-08-16 16:37:11 -07:00