FPGA/verilog-axi
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2 Commits

Author SHA1 Message Date
Alex Forencich
d274c73cb7 Add default_nettype none and resetall directives 2021-10-20 15:36:04 -07:00
Alex Forencich
5c2c6fd2bb Add AXI lite register interface modules 2021-08-29 19:09:52 -07:00