FPGA/verilog-axi
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4 Commits

Author SHA1 Message Date
Alex Forencich
e10a7ae88e Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 22:12:16 -08:00
Alex Forencich
293cfe153c Use start_soon instead of fork 2021-12-10 18:23:39 -08:00
Alex Forencich
fbb507be82 Remove deprecated assigments 2021-11-15 14:31:28 -08:00
Alex Forencich
5c2c6fd2bb Add AXI lite register interface modules 2021-08-29 19:09:52 -07:00