FPGA/verilog-axi
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3 Commits

Author SHA1 Message Date
Alex Forencich
818fac5daa Update signal names 2019-01-16 19:37:15 -08:00
Alex Forencich
523bf689d8 Add optional output pipeline register to AXI lite RAM 2019-01-09 00:25:40 -08:00
Alex Forencich
ad453b12db Add AXI lite RAM module and testbench 2018-08-14 23:49:40 -07:00