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Author SHA1 Message Date
Alex Forencich
0e36f647cb Add arbiter and priority encoder modules 2018-08-22 21:50:31 -07:00
Alex Forencich
82a13479e7 Add decode error tests 2018-08-22 20:43:28 -07:00
Alex Forencich
e696abbdff Add AXI lite shared interconnect module and testbench 2018-08-22 20:34:31 -07:00
Alex Forencich
2a4c63e859 Change default address width to 32 2018-08-21 22:38:32 -07:00
Alex Forencich
7c40254d7e Remove redundant testbenches 2018-08-21 22:27:47 -07:00
Alex Forencich
6a002e2ce0 Add CONVERT_NARROW_BURST and FORWARD_ID parameters to AXI adapter 2018-08-20 23:23:00 -07:00
Alex Forencich
b15e8d9f63 Add AXI adapters and testbenchs 2018-08-20 19:10:08 -07:00
Alex Forencich
160f20bc8c Change default awcache/arcache value 2018-08-17 16:29:12 -07:00
Alex Forencich
e06d607b85 Add AXI lite width adapter and testbenches 2018-08-16 16:37:11 -07:00
Alex Forencich
48577f3a2d Add simple register as a per-channel option to AXI register modules 2018-08-16 13:25:07 -07:00
Alex Forencich
d541c64bc0 Add AXI lite registers and testbenches 2018-08-16 13:01:45 -07:00
Alex Forencich
97cbbd1781 Don't crash when omitting read or write port connections 2018-08-16 12:50:14 -07:00
Alex Forencich
4adcf9c7d0 Add prot and resp signal encoding constants 2018-08-15 23:02:57 -07:00
Alex Forencich
ad453b12db Add AXI lite RAM module and testbench 2018-08-14 23:49:40 -07:00
Alex Forencich
57abfa66bc Add MyHDL AXI4 Lite master model, RAM model, and testbench 2018-08-14 23:49:11 -07:00
Alex Forencich
b8e6b30717 Don't use narrow bursts for setup and checking in AXI RAM testbench 2018-08-14 23:44:15 -07:00
Alex Forencich
5614f7dafe When pausing the AXI model, do not drop valid signals if they are asserted and waiting for a ready signal assert 2018-08-14 23:38:08 -07:00
Alex Forencich
09759518fc ID always zero if ID pins not connected 2018-08-14 21:48:24 -07:00
Alex Forencich
649179894a Remove unnecessary asserts 2018-08-14 21:46:05 -07:00
Alex Forencich
2113bb1795 Add AXI registers and testbenches 2018-08-13 23:36:47 -07:00
Alex Forencich
5f302d8106 Fix some more issues in AXI RAM module 2018-08-13 16:00:29 -07:00
Alex Forencich
66b20c171b Add AXI FIFOs and testbenches 2018-08-13 15:31:04 -07:00
Alex Forencich
a962dfce72 Properly handle read bursts in AXI model 2018-08-13 15:12:56 -07:00
Alex Forencich
7e18825ba2 Fix 4k align 2018-08-12 23:08:38 -07:00
Alex Forencich
aed7cf9d9b Print burst debugging information 2018-08-12 22:37:28 -07:00
Alex Forencich
ed27cebed8 Add max_burst_len parameter 2018-08-11 23:09:28 -07:00
Alex Forencich
e29114fe04 Check for disconnected ports 2018-08-11 23:09:00 -07:00
Alex Forencich
0cb456e047 Improve testbench and fix bugs in axi_ram 2018-08-11 22:32:05 -07:00
Alex Forencich
4ee04f6682 Support pausing channels in AXI models 2018-08-11 21:47:08 -07:00
Alex Forencich
048c0bb5e5 Updates for python 2 2018-08-06 15:02:59 -07:00
Alex Forencich
947e700dc2 Support omitting id signals 2018-08-02 17:27:40 -07:00
Alex Forencich
e78f865ddf Fix 4K boundary assert 2018-07-30 17:54:23 -07:00
Alex Forencich
f4cca52660 Initial commit 2018-07-29 19:04:30 -07:00