FPGA/verilog-axi
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-axi.git synced 2025-01-28 07:02:56 +08:00
Code Issues Projects Releases Wiki Activity
181 Commits 2 Branches 0 Tags
Commit Graph

11 Commits

Author SHA1 Message Date
Alex Forencich
e10a7ae88e Rework parameter handling in testbench makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 22:12:16 -08:00
Alex Forencich
293cfe153c Use start_soon instead of fork 2021-12-10 18:23:39 -08:00
Alex Forencich
fbb507be82 Remove deprecated assigments 2021-11-15 14:31:28 -08:00
Alex Forencich
51caad0810 Extract port counts 2021-06-01 13:22:48 -07:00
Alex Forencich
a45c36e802 Update testbenches 2021-04-12 22:55:38 -07:00
Alex Forencich
bb30f0a50f Extract parameter values from cocotb.top 2021-03-22 18:07:04 -07:00
Alex Forencich
be689ebb77 Update testbenches 2021-03-06 19:55:50 -08:00
Alex Forencich
03a78413c5 Rework sim_build output directory, fix default makefile target 2020-12-29 16:09:02 -08:00
Alex Forencich
db58c836f6 Use absolute path to test directory 2020-12-28 18:52:47 -08:00
Alex Forencich
ca7f0131ea Remove unnecessary __init__.py files 2020-12-15 18:59:49 -08:00
Alex Forencich
72f5a2d1cb Add cocotb testbenches 2020-12-04 15:32:14 -08:00