FPGA/verilog-axi
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4 Commits

Author SHA1 Message Date
Alex Forencich
eda769d167 Update CI configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-26 13:00:03 -08:00
Alex Forencich
db826e489b Set algorithm for pytest-split 2021-08-01 01:19:07 -07:00
Alex Forencich
ac69ddfa22 Update github actions 2021-01-16 13:38:10 -08:00
Alex Forencich
face7776d4 Add Github Actions regresion testing 2020-12-04 15:50:56 -08:00