FPGA/verilog-axi
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4 Commits

Author SHA1 Message Date
Alex Forencich
275cb09205 Minor reorganization 2018-12-06 17:19:30 -08:00
Alex Forencich
e5e2aa8867 Use correct parameter 2018-12-06 01:21:42 -08:00
Alex Forencich
e7b6f43c8c Fix multi-driven net issue 2018-12-04 21:03:39 -08:00
Alex Forencich
43234018cd Add AXI read DMA module and testbenches 2018-12-03 23:29:22 -08:00