23 Commits

Author	SHA1	Message	Date
Alex Forencich	fceea6f8d8	Add output FIFOs to DMA engines	2021-08-03 01:53:18 -07:00
Alex Forencich	ee9c719bf4	Add error reporting to DMA modules	2021-08-01 10:59:38 -07:00
Alex Forencich	0afd441eba	Fix active operation count logic	2021-02-17 21:14:51 -08:00
Alex Forencich	e5f5b1c352	Remove unused regs	2021-02-17 18:30:55 -08:00
Alex Forencich	68387161d4	Track active operation count to prevent status FIFO overflow	2021-02-17 18:29:44 -08:00
Alex Forencich	83b5d30347	Rewrite resets	2021-02-17 18:06:47 -08:00
Alex Forencich	c7d74b6425	Fix unaligned backpressure issue in AXI DMA write module	2020-11-14 20:12:24 -08:00
Alex Forencich	0eda0767af	Rewrite 4K address boundary crossing checks	2020-11-11 22:29:40 -08:00
Alex Forencich	4e95fb3677	Bypass check when unneeded	2019-10-30 22:57:56 -07:00
Alex Forencich	521c6d909e	Include instance names in error messages	2019-07-25 16:33:27 -07:00
Alex Forencich	62dbc043e2	Add parameter documentation	2019-07-24 17:49:48 -07:00
Alex Forencich	f6acefbf94	Simplify logic	2019-06-22 01:51:06 -07:00
Alex Forencich	ebbaea908b	Add strb_offset_mask_reg	2019-06-22 00:13:11 -07:00
Alex Forencich	b1edaf1ae4	Optimize check	2019-06-22 00:05:15 -07:00
Alex Forencich	6ed937d521	Add zero offset reg	2019-06-21 20:42:20 -07:00
Alex Forencich	967aa8c2f3	Mask instead of barrel shift	2019-06-21 20:38:09 -07:00
Alex Forencich	435f0b8749	Timing optimization of wstrb	2019-06-21 12:04:58 -07:00
Alex Forencich	834d6a4b2d	Improve timing for unaligned operations (shift_axis_extra_cycle)	2019-06-15 21:27:41 -07:00
Alex Forencich	f128190130	Ensure transfer is terminated at the end of the input frame	2019-03-13 14:48:05 -07:00
Alex Forencich	e71a62e6a1	Fix backpressure issue	2019-03-07 17:45:25 -08:00
Alex Forencich	04dd6a34d7	Fix combinatorial loop	2019-02-20 18:48:27 -08:00
Alex Forencich	7654d874ae	Fix out of range access due to off by one error	2019-02-11 19:30:57 -08:00
Alex Forencich	41f8667310	Add AXI write DMA module and testbenches	2018-12-27 14:15:51 -08:00