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  • fb13076e18
         Merge b31d5137adc6d4955e84425747de170dd61fd702 into 38915fb5330cb8270b454afc0140a94489dc56db Yuji YAMADA 2024-12-05 16:52:57 +09:00
  • b31d5137ad Prevent CL_M_COUNT-1 from being -1, and then the vector won't become ascending range. offnaria 2024-12-05 16:37:28 +09:00
  • 057254e6a5
         Merge 76e00b64fdccecaf70277f6531f952d45818bd50 into 38915fb5330cb8270b454afc0140a94489dc56db aharrysrc 2024-12-03 18:28:55 +00:00
  • 76e00b64fd start transaction even when it's a decerr to avoid trans_count_reg getting out of sync Allison Harry 2024-12-03 13:23:15 -05:00
  • 98fa139be6
         Merge e0a2c846e920f038f167f3e53fe56dd4e3122720 into 38915fb5330cb8270b454afc0140a94489dc56db Dylan Barrie 2023-12-07 09:02:44 +00:00
  • e0a2c846e9 Add explicit python3 prefix to all python paths in test suite Dylan Barrie 2023-12-07 00:59:45 -08:00
  • 7f6f4fa313
         Merge f104c85fe7848ef012634722938d8b49e6d8fb4a into 38915fb5330cb8270b454afc0140a94489dc56db Dan Gisselquist 2023-04-03 09:02:53 +02:00
  • 2908c54304
         Merge aa67b30e5b596459760bc35b3c4e78ee2b270d98 into 38915fb5330cb8270b454afc0140a94489dc56db Jiaxun Yang 2023-04-03 09:02:53 +02:00
  • 98e620010a
         Merge d70259be023fabf3a44a6e1d378604de896d43ba into 38915fb5330cb8270b454afc0140a94489dc56db bunnie 2023-04-03 09:02:53 +02:00
  • a30fb374da
         Merge 3fd19a7caf4a4227e3964334fdb379a841cdb38a into 38915fb5330cb8270b454afc0140a94489dc56db bunnie 2023-04-03 09:02:53 +02:00
  • d495f25c4e
         Merge 5b255a3cb485352647e580cb7c0ca57d17d74f26 into 38915fb5330cb8270b454afc0140a94489dc56db Ben Reynwar 2023-04-03 09:02:53 +02:00
  • 1fa1fe7a20
         Merge 38dea12728ce070e3f999a981a332e796e956095 into 38915fb5330cb8270b454afc0140a94489dc56db Alex Lao 2023-03-30 09:40:52 -04:00
  • 38915fb533 Fix reset CDC in AXI VFIFO master Alex Forencich 2023-03-30 00:12:13 -07:00
  • 59d37ee850 Add AXI virtual FIFO Alex Forencich 2023-03-28 20:59:47 -07:00
  • 99ff2e81b7 Update cocotbext-axi version Alex Forencich 2023-03-28 19:15:40 -07:00
  • 38dea12728 Workaround AXI_ADDR_BIT_OFFSET and AXIL_ADDR_BIT_OFFSET error in ModelSim by using relative part selects Alex Lao 2023-03-09 23:24:38 -05:00
  • c4e502d349 Workaround AXI_ADDR_BIT_OFFSET and AXIL_ADDR_BIT_OFFSET part select Alex Lao 2023-03-05 14:30:28 -05:00
  • 5b255a3cb4 Minor changes to get axil_crossbar test working in verilator. Mostly adding lint_off. Ben Reynwar 2023-03-01 09:51:54 -07:00
  • 00c200f881 Remove recursively-expanded macros for module parameters in makefiles Alex Forencich 2023-02-17 16:18:44 -08:00
  • de3ec216a0 Fix min address width checks in AXI lite components Alex Forencich 2023-02-13 13:18:24 -08:00
  • 0cba4e1917 Update ubuntu version in CI Alex Forencich 2023-02-13 13:03:26 -08:00
  • e10a7ae88e Rework parameter handling in testbench makefiles Alex Forencich 2023-01-29 22:12:16 -08:00
  • eda769d167 Update CI configuration Alex Forencich 2023-01-26 13:00:03 -08:00
  • 7b2c99e731 Fix unaligned operation handling in AXI to AXIL adapter Alex Forencich 2023-01-26 12:58:39 -08:00
  • 211f674603 Fix unaligned operation handling in AXI adapter Alex Forencich 2023-01-26 12:58:03 -08:00
  • 3dc4ca92f6 Improve unaligned operation handling in AXIL adapter Alex Forencich 2023-01-25 21:08:32 -08:00
  • f521fb6435 Update timing constraints to handle clocks from OOC IP that are not constrained during synthesis Alex Forencich 2023-01-17 13:40:36 -08:00
  • 3fd19a7caf add initialization file, cleanup address widths buncram 2022-11-12 01:15:03 +08:00
  • d70259be02 fix numerical overflow in bit shift operation bunnie 2022-12-18 16:03:10 +08:00
  • d699cd4b21 added pragmas to disable verilator lint warnings Jamey Hicks 2022-11-11 12:35:41 -05:00
  • 441e367051 revise rtl/axil_reg_if_wr.v for DDR Zhizhen Zhong 2022-11-08 23:07:02 -05:00
  • d1fd8e54b9 fix vivado synthesis problems in axil_reg_if_wr.v Jamey Hicks 2022-11-04 13:27:48 -04:00
  • a91e98c105 Update package versions Alex Forencich 2022-09-07 20:03:34 -07:00
  • 4f1462abb8 axi_adapter: make both expand and non-expand code always compilable by conditioning parameter values Ilia Sergachev 2022-08-07 15:34:23 +02:00
  • 25912d48fe Lock package versions Alex Forencich 2021-12-27 16:54:26 -08:00
  • c7ef809417 Specify min tox and venv versions Alex Forencich 2021-12-27 16:53:49 -08:00
  • d11a48c94b Use available python 3 Alex Forencich 2021-12-27 16:52:07 -08:00
  • 293cfe153c Use start_soon instead of fork Alex Forencich 2021-12-10 18:23:39 -08:00
  • fbb507be82 Remove deprecated assigments Alex Forencich 2021-11-15 14:31:28 -08:00
  • 078bbc8f07 Fix typos Alex Forencich 2021-11-07 17:50:23 -08:00
  • b4bdfb6542 Add FIFO output register in AXI lite crossbar modules Alex Forencich 2021-11-06 15:20:19 -07:00
  • 0b16849b57 Add attributes to RAMs for proper synthesis in Quartus Alex Forencich 2021-11-04 20:43:13 -07:00
  • d274c73cb7 Add default_nettype none and resetall directives Alex Forencich 2021-10-20 15:36:04 -07:00
  • 302a23209f Add missing wires Alex Forencich 2021-10-20 13:00:44 -07:00
  • aa67b30e5b Fix readme typo Jiaxun Yang 2021-10-12 15:17:00 +01:00
  • a6a9a2ebd8 Update readme Alex Forencich 2021-08-29 19:16:43 -07:00
  • 5c2c6fd2bb Add AXI lite register interface modules Alex Forencich 2021-08-29 19:09:52 -07:00
  • 6b108481b8 Update interconnect address handling Alex Forencich 2021-08-26 16:48:31 -07:00
  • fe283eee02 Update readme Alex Forencich 2021-08-11 01:25:42 -07:00
  • 26534e75ce Add AXI lite crossbar module and testbench Alex Forencich 2021-08-11 01:23:14 -07:00
  • 39dc8662b6 Remove duplicate code Alex Forencich 2021-08-11 01:16:02 -07:00
  • bf3143a79f Fix test name Alex Forencich 2021-08-03 01:54:00 -07:00
  • fceea6f8d8 Add output FIFOs to DMA engines Alex Forencich 2021-08-03 01:53:18 -07:00
  • ee9c719bf4 Add error reporting to DMA modules Alex Forencich 2021-08-01 10:59:38 -07:00
  • db826e489b Set algorithm for pytest-split Alex Forencich 2021-08-01 01:19:07 -07:00
  • 2a7d190eb4 Update test durations Alex Forencich 2021-06-03 13:48:33 -07:00
  • 5063aeadcd Remove string parameters Alex Forencich 2021-06-02 17:04:53 -07:00
  • 51caad0810 Extract port counts Alex Forencich 2021-06-01 13:22:48 -07:00
  • a852697707 Fix instance names in wrappers Alex Forencich 2021-06-01 13:18:11 -07:00
  • 9c4012f58d Reorganize timing constraints Alex Forencich 2021-05-20 15:15:51 -07:00
  • 314ea7dbf9 Update readme Alex Forencich 2021-04-12 22:55:49 -07:00
  • a45c36e802 Update testbenches Alex Forencich 2021-04-12 22:55:38 -07:00
  • bf2a779e48 Rewrite test Alex Forencich 2021-03-24 22:00:20 -07:00
  • bb30f0a50f Extract parameter values from cocotb.top Alex Forencich 2021-03-22 18:07:04 -07:00
  • 1f3920afcc Use release version of cocotb for CI Alex Forencich 2021-03-17 19:10:04 -07:00
  • be689ebb77 Update testbenches Alex Forencich 2021-03-06 19:55:50 -08:00
  • 0afd441eba Fix active operation count logic Alex Forencich 2021-02-17 21:14:51 -08:00
  • e5f5b1c352 Remove unused regs Alex Forencich 2021-02-17 18:30:55 -08:00
  • 68387161d4 Track active operation count to prevent status FIFO overflow Alex Forencich 2021-02-17 18:29:44 -08:00
  • 83b5d30347 Rewrite resets Alex Forencich 2021-02-17 18:06:47 -08:00
  • ac69ddfa22 Update github actions Alex Forencich 2021-01-16 13:38:10 -08:00
  • 03a78413c5 Rework sim_build output directory, fix default makefile target Alex Forencich 2020-12-29 16:09:02 -08:00
  • c029f2d0b4 Proof of concept CLI cli_tb Alex Forencich 2020-12-28 18:55:57 -08:00
  • 3a59569105 Remove extraneous import Alex Forencich 2020-12-28 18:53:00 -08:00
  • db58c836f6 Use absolute path to test directory Alex Forencich 2020-12-28 18:52:47 -08:00
  • 9ab1fb44b1 Convert send/recv to blocking Alex Forencich 2020-12-18 16:50:50 -08:00
  • ca7f0131ea Remove unnecessary __init__.py files Alex Forencich 2020-12-15 18:59:49 -08:00
  • be767f8ee7 Update readme Alex Forencich 2020-12-04 16:18:28 -08:00
  • f8ff8a98d5 Remove README symlink Alex Forencich 2020-12-04 16:15:32 -08:00
  • face7776d4 Add Github Actions regresion testing Alex Forencich 2020-12-04 15:50:56 -08:00
  • bd4e574b36 Add posargs to tox.ini Alex Forencich 2020-12-04 15:49:51 -08:00
  • 5d2389fd81 Add test durations for pytest-split Alex Forencich 2020-12-04 15:41:35 -08:00
  • de53699ed4 Add top-level makefile Alex Forencich 2020-12-04 15:41:10 -08:00
  • 72f5a2d1cb Add cocotb testbenches Alex Forencich 2020-12-04 15:32:14 -08:00
  • 8fb827a18b Add tox and pytest configuration Alex Forencich 2020-12-04 15:30:48 -08:00
  • 3d2364e19e Add wrapper generators Alex Forencich 2020-12-04 15:21:14 -08:00
  • e4c4222fa9 Use wlast instead of awlen to detect end of write burst Alex Forencich 2020-11-15 11:26:39 -08:00
  • c7d74b6425 Fix unaligned backpressure issue in AXI DMA write module Alex Forencich 2020-11-14 20:12:24 -08:00
  • 0eda0767af Rewrite 4K address boundary crossing checks Alex Forencich 2020-11-11 22:29:40 -08:00
  • f104c85fe7 Updated AXI-lite RAM to pass a formal verification check ZipCPU 2020-11-06 16:58:31 -05:00
  • cd06f0b7dc Drop entire write operation on address decode fail in axi_interconnect Alex Forencich 2020-10-19 00:13:40 -07:00
  • 2c6185c0a5 Rewrite resets Alex Forencich 2020-08-27 13:26:03 -07:00
  • 00e2756385 Rewrite priority encoder to remove recusive construction Alex Forencich 2020-08-17 18:28:59 -07:00
  • c1f31e537e Remove unnecessary wait state when output is ready Alex Forencich 2020-08-17 00:13:02 -07:00
  • ba0b96ca34 Use logical operators Alex Forencich 2020-08-17 00:11:52 -07:00
  • 8b789c89ae Reset count_reg in axi_fifo_rd Alex Forencich 2020-08-17 00:09:06 -07:00
  • 9b03dfdb1a Fix backpressure bug Alex Forencich 2020-04-12 23:33:15 -07:00
  • 8ff77c8ae7 Fix reg name Alex Forencich 2020-04-12 22:13:12 -07:00
  • e55e42c6f1 Fix counter reset kermitchen 2019-12-12 14:03:17 +08:00
  • 82030d3720 Use correct RAM size for initialization Alex Forencich 2019-11-24 15:38:10 -08:00