verilog-axi

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66b20c171b Add AXI FIFOs and testbenches Alex Forencich 2018-08-13 15:31:04 -07:00
a962dfce72 Properly handle read bursts in AXI model Alex Forencich 2018-08-13 15:12:56 -07:00
7e18825ba2 Fix 4k align Alex Forencich 2018-08-12 23:08:38 -07:00
aed7cf9d9b Print burst debugging information Alex Forencich 2018-08-12 22:37:28 -07:00
ed27cebed8 Add max_burst_len parameter Alex Forencich 2018-08-11 23:09:28 -07:00
e29114fe04 Check for disconnected ports Alex Forencich 2018-08-11 23:09:00 -07:00
0cb456e047 Improve testbench and fix bugs in axi_ram Alex Forencich 2018-08-11 22:32:05 -07:00
4ee04f6682 Support pausing channels in AXI models Alex Forencich 2018-08-11 21:47:08 -07:00
048c0bb5e5 Updates for python 2 Alex Forencich 2018-08-06 15:02:59 -07:00
947e700dc2 Support omitting id signals Alex Forencich 2018-08-02 17:27:40 -07:00
e78f865ddf Fix 4K boundary assert Alex Forencich 2018-07-30 17:54:23 -07:00
f4cca52660 Initial commit Alex Forencich 2018-07-29 19:04:30 -07:00