mirror of
https://github.com/alexforencich/verilog-axi.git
synced 2025-01-28 07:02:56 +08:00
88 lines
4.3 KiB
Tcl
88 lines
4.3 KiB
Tcl
# Copyright (c) 2023 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# AXI virtual FIFO timing constraints
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foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == axi_vfifo || REF_NAME == axi_vfifo)}] {
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puts "Inserting timing constraints for axil_vfifo instance $inst"
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proc constrain_sync_chain {inst driver args} {
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set sync_ffs [get_cells -hier [concat $driver $args] -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set src_clk [get_clocks -of_objects [get_cells "$inst/$driver"]]
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set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}]
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set_max_delay -from [get_cells "$inst/$driver"] -to [get_cells "$inst/[lindex $args 0]"] -datapath_only $src_clk_period
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}
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}
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proc constrain_sync_chain_async {inst driver args} {
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set sync_ffs [get_cells -hier [concat $driver $args] -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set_false_path -to [get_pins "$inst/$driver/D"]
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}
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}
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# control
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constrain_sync_chain $inst "cfg_enable_reg_reg" "axi_ch[*].ch_cfg_enable_sync_1_reg_reg" "axi_ch[*].ch_cfg_enable_sync_2_reg_reg"
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constrain_sync_chain $inst "cfg_reset_reg_reg" "axi_ch[*].ch_cfg_reset_sync_1_reg_reg" "axi_ch[*].ch_cfg_reset_sync_2_reg_reg"
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set sync_ffs [get_cells "$inst/cfg_fifo_base_addr_reg_reg[*] $inst/axi_ch[*].axi_vfifo_raw_inst/fifo_base_addr_reg_reg[*]"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set src_clk [get_clocks -of_objects [get_cells "$inst/cfg_fifo_base_addr_reg_reg[*]"]]
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set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}]
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set_max_delay -from [get_cells "$inst/cfg_fifo_base_addr_reg_reg[*]"] -to [get_cells "$inst/axi_ch[*].axi_vfifo_raw_inst/fifo_base_addr_reg_reg[*]"] -datapath_only $src_clk_period
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}
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set sync_ffs [get_cells "$inst/cfg_fifo_size_mask_reg_reg[*] $inst/axi_ch[*].axi_vfifo_raw_inst/fifo_size_mask_reg_reg[*]"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set src_clk [get_clocks -of_objects [get_cells "$inst/cfg_fifo_size_mask_reg_reg[*]"]]
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set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 1.0}]
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set_max_delay -from [get_cells "$inst/cfg_fifo_size_mask_reg_reg[*]"] -to [get_cells "$inst/axi_ch[*].axi_vfifo_raw_inst/fifo_size_mask_reg_reg[*]"] -datapath_only $src_clk_period
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}
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# status
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constrain_sync_chain $inst "sts_sync_flag_reg_reg" "axi_ch[*].ch_sts_flag_sync_1_reg_reg" "axi_ch[*].ch_sts_flag_sync_2_reg_reg"
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constrain_sync_chain_async $inst "sts_fifo_occupancy_sync_reg_reg[*]"
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constrain_sync_chain_async $inst "sts_fifo_empty_sync_1_reg_reg[*]" "sts_fifo_empty_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "sts_fifo_full_sync_1_reg_reg[*]" "sts_fifo_full_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "sts_reset_sync_1_reg_reg[*]" "sts_reset_sync_2_reg_reg[*]"
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constrain_sync_chain_async $inst "sts_active_sync_1_reg_reg[*]" "sts_active_sync_2_reg_reg[*]"
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constrain_sync_chain $inst "sts_hdr_parity_err_reg_reg" "sts_hdr_parity_err_sync_1_reg_reg" "sts_hdr_parity_err_sync_2_reg_reg"
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}
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