mirror of
https://github.com/alexforencich/verilog-axi.git
synced 2025-02-04 07:12:57 +08:00
686 lines
22 KiB
Python
686 lines
22 KiB
Python
"""
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Copyright (c) 2023 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import itertools
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import logging
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import os
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import random
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiBus, AxiRam
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from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 8, units="ns").start())
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# streaming data in
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cocotb.start_soon(Clock(dut.s_axis_clk, 6, units="ns").start())
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self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "s_axis"), dut.s_axis_clk, dut.s_axis_rst_out)
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# streaming data out
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cocotb.start_soon(Clock(dut.m_axis_clk, 6, units="ns").start())
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self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.m_axis_clk, dut.m_axis_rst_out)
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# AXI interfaces
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self.axi_ram = []
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for ch in dut.axi_ch:
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cocotb.start_soon(Clock(ch.ch_clk, 3, units="ns").start())
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ram = AxiRam(AxiBus.from_prefix(ch.axi_vfifo_raw_inst, "m_axi"), ch.ch_clk, ch.ch_rst, size=2**16)
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self.axi_ram.append(ram)
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dut.cfg_fifo_base_addr.setimmediatevalue(0)
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dut.cfg_fifo_size_mask.setimmediatevalue(0)
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dut.cfg_enable.setimmediatevalue(0)
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dut.cfg_reset.setimmediatevalue(0)
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def set_idle_generator(self, generator=None):
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if generator:
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self.source.set_pause_generator(generator())
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for ram in self.axi_ram:
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ram.write_if.b_channel.set_pause_generator(generator())
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ram.read_if.r_channel.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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self.sink.set_pause_generator(generator())
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for ram in self.axi_ram:
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ram.write_if.aw_channel.set_pause_generator(generator())
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ram.write_if.w_channel.set_pause_generator(generator())
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ram.read_if.ar_channel.set_pause_generator(generator())
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def set_stream_idle_generator(self, generator=None):
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if generator:
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self.source.set_pause_generator(generator())
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def set_stream_backpressure_generator(self, generator=None):
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if generator:
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self.sink.set_pause_generator(generator())
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def set_axi_0_idle_generator(self, generator=None):
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if generator:
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self.axi_ram[0].write_if.b_channel.set_pause_generator(generator())
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self.axi_ram[0].read_if.r_channel.set_pause_generator(generator())
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def set_axi_0_backpressure_generator(self, generator=None):
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if generator:
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self.axi_ram[0].write_if.aw_channel.set_pause_generator(generator())
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self.axi_ram[0].write_if.w_channel.set_pause_generator(generator())
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self.axi_ram[0].read_if.ar_channel.set_pause_generator(generator())
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def set_axi_idle_generator(self, generator=None):
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if generator:
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for ram in self.axi_ram:
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ram.write_if.b_channel.set_pause_generator(generator())
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ram.read_if.r_channel.set_pause_generator(generator())
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def set_axi_backpressure_generator(self, generator=None):
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if generator:
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for ram in self.axi_ram:
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ram.write_if.aw_channel.set_pause_generator(generator())
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ram.write_if.w_channel.set_pause_generator(generator())
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ram.read_if.ar_channel.set_pause_generator(generator())
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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self.dut.s_axis_rst.setimmediatevalue(0)
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self.dut.m_axis_rst.setimmediatevalue(0)
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for ram in self.axi_ram:
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ram.write_if.reset.setimmediatevalue(0)
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for k in range(10):
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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self.dut.s_axis_rst.value = 1
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self.dut.m_axis_rst.value = 1
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for ram in self.axi_ram:
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ram.write_if.reset.value = 1
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for k in range(10):
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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self.dut.s_axis_rst.value = 0
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self.dut.m_axis_rst.value = 0
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for ram in self.axi_ram:
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ram.write_if.reset.value = 0
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for k in range(10):
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await RisingEdge(self.dut.clk)
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async def reset_source(self):
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self.dut.s_axis_rst.setimmediatevalue(0)
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for k in range(10):
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await RisingEdge(self.dut.s_axis_clk)
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self.dut.s_axis_rst.value = 1
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for k in range(10):
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await RisingEdge(self.dut.s_axis_clk)
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self.dut.s_axis_rst.value = 0
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for k in range(10):
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await RisingEdge(self.dut.s_axis_clk)
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async def reset_sink(self):
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self.dut.m_axis_rst.setimmediatevalue(0)
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for k in range(10):
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await RisingEdge(self.dut.m_axis_clk)
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self.dut.m_axis_rst.value = 1
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for k in range(10):
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await RisingEdge(self.dut.m_axis_clk)
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self.dut.m_axis_rst.value = 0
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for k in range(10):
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await RisingEdge(self.dut.m_axis_clk)
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async def reset_axi_0(self):
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self.axi_ram[0].write_if.reset.setimmediatevalue(0)
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for k in range(10):
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await RisingEdge(self.dut.clk)
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self.axi_ram[0].write_if.reset.value = 1
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for k in range(10):
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await RisingEdge(self.dut.clk)
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self.axi_ram[0].write_if.reset.value = 0
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for k in range(10):
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await RisingEdge(self.dut.clk)
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async def reset_axi(self):
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for ram in self.axi_ram:
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ram.write_if.reset.setimmediatevalue(0)
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for k in range(10):
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await RisingEdge(self.dut.clk)
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for ram in self.axi_ram:
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ram.write_if.reset.value = 1
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for k in range(10):
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await RisingEdge(self.dut.clk)
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for ram in self.axi_ram:
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ram.write_if.reset.value = 0
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for k in range(10):
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await RisingEdge(self.dut.clk)
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async def reset_cfg(self):
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self.dut.cfg_reset.setimmediatevalue(0)
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for k in range(10):
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await RisingEdge(self.dut.clk)
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self.dut.cfg_reset.value = 1
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for k in range(10):
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await RisingEdge(self.dut.clk)
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self.dut.cfg_reset.value = 0
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for k in range(10):
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await RisingEdge(self.dut.clk)
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async def run_test(dut, payload_lengths=None, payload_data=None, space=False,
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stream_idle_inserter=None, stream_backpressure_inserter=None,
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axi_0_idle_inserter=None, axi_0_backpressure_inserter=None,
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axi_idle_inserter=None, axi_backpressure_inserter=None):
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tb = TB(dut)
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id_count = 2**len(tb.source.bus.tid)
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cur_id = 1
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await tb.reset()
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tb.set_stream_idle_generator(stream_idle_inserter)
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tb.set_stream_backpressure_generator(stream_backpressure_inserter)
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tb.set_axi_idle_generator(axi_idle_inserter)
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tb.set_axi_backpressure_generator(axi_backpressure_inserter)
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tb.set_axi_0_backpressure_generator(axi_0_backpressure_inserter)
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tb.set_axi_0_idle_generator(axi_0_idle_inserter)
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dut.cfg_fifo_base_addr.setimmediatevalue(0)
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dut.cfg_fifo_size_mask.setimmediatevalue(2**16-1)
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dut.cfg_enable.setimmediatevalue(1)
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test_frames = []
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for test_data in [payload_data(x) for x in payload_lengths()]:
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test_frame = AxiStreamFrame(test_data)
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test_frame.tid = cur_id
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test_frame.tdest = cur_id
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test_frames.append(test_frame)
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await tb.source.send(test_frame)
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cur_id = (cur_id + 1) % id_count
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if space:
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for k in range(1000):
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await RisingEdge(dut.clk)
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if dut.m_axis_tvalid.value.integer and dut.m_axis_tready.value.integer and dut.m_axis_tlast.value.integer:
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break
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for test_frame in test_frames:
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_frame.tdata
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assert rx_frame.tid == test_frame.tid
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assert rx_frame.tdest == test_frame.tdest
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assert not rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.s_axis_clk)
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await RisingEdge(dut.s_axis_clk)
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async def run_test_tuser_assert(dut):
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tb = TB(dut)
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byte_lanes = tb.source.byte_lanes
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await tb.reset()
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dut.cfg_fifo_base_addr.setimmediatevalue(0)
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dut.cfg_fifo_size_mask.setimmediatevalue(2**16-1)
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dut.cfg_enable.setimmediatevalue(1)
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32*byte_lanes))
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test_frame = AxiStreamFrame(test_data, tuser=1)
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await tb.source.send(test_frame)
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_data
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assert rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.s_axis_clk)
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await RisingEdge(dut.s_axis_clk)
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async def run_test_init_sink_pause(dut):
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tb = TB(dut)
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byte_lanes = tb.source.byte_lanes
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await tb.reset()
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dut.cfg_fifo_base_addr.setimmediatevalue(0)
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dut.cfg_fifo_size_mask.setimmediatevalue(2**16-1)
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dut.cfg_enable.setimmediatevalue(1)
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tb.sink.pause = True
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 1024*byte_lanes))
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test_frame = AxiStreamFrame(test_data)
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await tb.source.send(test_frame)
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for k in range(256):
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await RisingEdge(dut.s_axis_clk)
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tb.sink.pause = False
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_data
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assert not rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.s_axis_clk)
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await RisingEdge(dut.s_axis_clk)
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async def run_test_init_sink_pause_reset(dut, reset_type=TB.reset):
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tb = TB(dut)
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byte_lanes = tb.source.byte_lanes
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await tb.reset()
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dut.cfg_fifo_base_addr.setimmediatevalue(0)
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dut.cfg_fifo_size_mask.setimmediatevalue(2**16-1)
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dut.cfg_enable.setimmediatevalue(1)
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tb.sink.pause = True
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 1024*byte_lanes))
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test_frame = AxiStreamFrame(test_data)
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await tb.source.send(test_frame)
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for k in range(256):
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await RisingEdge(dut.s_axis_clk)
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await reset_type(tb)
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tb.sink.pause = False
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for k in range(2048):
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await RisingEdge(dut.s_axis_clk)
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assert tb.sink.idle()
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assert tb.sink.empty()
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await tb.source.send(test_frame)
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_data
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assert not rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.s_axis_clk)
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await RisingEdge(dut.s_axis_clk)
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async def run_test_shift_in_reset(dut, reset_type=TB.reset):
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tb = TB(dut)
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byte_lanes = tb.source.byte_lanes
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await tb.reset()
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dut.cfg_fifo_base_addr.setimmediatevalue(0)
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dut.cfg_fifo_size_mask.setimmediatevalue(2**16-1)
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dut.cfg_enable.setimmediatevalue(1)
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 1024*byte_lanes))
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test_frame = AxiStreamFrame(test_data)
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await tb.source.send(test_frame)
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for k in range(256):
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await RisingEdge(dut.s_axis_clk)
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await reset_type(tb)
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for k in range(2048):
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await RisingEdge(dut.s_axis_clk)
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assert tb.sink.idle()
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assert tb.sink.empty()
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await tb.source.send(test_frame)
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_data
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assert not rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.s_axis_clk)
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await RisingEdge(dut.s_axis_clk)
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async def run_test_shift_out_reset(dut, reset_type=TB.reset):
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tb = TB(dut)
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byte_lanes = tb.source.byte_lanes
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await tb.reset()
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dut.cfg_fifo_base_addr.setimmediatevalue(0)
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dut.cfg_fifo_size_mask.setimmediatevalue(2**16-1)
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dut.cfg_enable.setimmediatevalue(1)
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 1024*byte_lanes))
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test_frame = AxiStreamFrame(test_data)
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await tb.source.send(test_frame)
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await RisingEdge(dut.m_axis_tvalid)
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for k in range(8):
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await RisingEdge(dut.s_axis_clk)
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await reset_type(tb)
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for k in range(2048):
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await RisingEdge(dut.s_axis_clk)
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assert tb.sink.idle()
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assert tb.sink.empty()
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await tb.source.send(test_frame)
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_data
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assert not rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.s_axis_clk)
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await RisingEdge(dut.s_axis_clk)
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async def run_test_overflow(dut):
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tb = TB(dut)
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await tb.reset()
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dut.cfg_fifo_base_addr.setimmediatevalue(0)
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dut.cfg_fifo_size_mask.setimmediatevalue(2**16-1)
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dut.cfg_enable.setimmediatevalue(1)
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tb.sink.pause = True
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ram_size = 2**tb.axi_ram[0].write_if.address_width*len(tb.axi_ram)
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test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 2*ram_size))
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test_frame = AxiStreamFrame(test_data)
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await tb.source.send(test_frame)
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for k in range(2048):
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await RisingEdge(dut.s_axis_clk)
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tb.sink.pause = False
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rx_frame = await tb.sink.recv()
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assert rx_frame.tdata == test_data
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assert not rx_frame.tuser
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assert tb.sink.empty()
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await RisingEdge(dut.s_axis_clk)
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await RisingEdge(dut.s_axis_clk)
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async def run_stress_test(dut, space=False,
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stream_idle_inserter=None, stream_backpressure_inserter=None,
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axi_0_idle_inserter=None, axi_0_backpressure_inserter=None,
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axi_idle_inserter=None, axi_backpressure_inserter=None):
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tb = TB(dut)
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byte_lanes = tb.source.byte_lanes
|
|
id_count = 2**len(tb.source.bus.tid)
|
|
|
|
cur_id = 1
|
|
|
|
await tb.reset()
|
|
|
|
dut.cfg_fifo_base_addr.setimmediatevalue(0)
|
|
dut.cfg_fifo_size_mask.setimmediatevalue(2**16-1)
|
|
dut.cfg_enable.setimmediatevalue(1)
|
|
|
|
tb.set_stream_idle_generator(stream_idle_inserter)
|
|
tb.set_stream_backpressure_generator(stream_backpressure_inserter)
|
|
tb.set_axi_idle_generator(axi_idle_inserter)
|
|
tb.set_axi_backpressure_generator(axi_backpressure_inserter)
|
|
tb.set_axi_0_backpressure_generator(axi_0_backpressure_inserter)
|
|
tb.set_axi_0_idle_generator(axi_0_idle_inserter)
|
|
|
|
test_frames = []
|
|
|
|
for k in range(128):
|
|
length = random.randint(1, byte_lanes*16)
|
|
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
|
test_frame = AxiStreamFrame(test_data)
|
|
test_frame.tid = cur_id
|
|
test_frame.tdest = cur_id
|
|
|
|
test_frames.append(test_frame)
|
|
await tb.source.send(test_frame)
|
|
|
|
cur_id = (cur_id + 1) % id_count
|
|
|
|
if space:
|
|
for k in range(1000):
|
|
await RisingEdge(dut.clk)
|
|
|
|
if dut.m_axis_tvalid.value.integer and dut.m_axis_tready.value.integer and dut.m_axis_tlast.value.integer:
|
|
break
|
|
|
|
for test_frame in test_frames:
|
|
rx_frame = await tb.sink.recv()
|
|
|
|
assert rx_frame.tdata == test_frame.tdata
|
|
assert rx_frame.tid == test_frame.tid
|
|
assert rx_frame.tdest == test_frame.tdest
|
|
assert not rx_frame.tuser
|
|
|
|
assert tb.sink.empty()
|
|
|
|
await RisingEdge(dut.s_axis_clk)
|
|
await RisingEdge(dut.s_axis_clk)
|
|
|
|
|
|
def cycle_pause():
|
|
return itertools.cycle([1, 1, 1, 0])
|
|
|
|
|
|
def size_list():
|
|
data_width = len(cocotb.top.m_axis_tdata)
|
|
byte_width = data_width // 8
|
|
return list(range(1, byte_width*4+1))+list(range(byte_width, byte_width*32, byte_width))+[2**14]+[1]*64
|
|
|
|
|
|
def incrementing_payload(length):
|
|
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
|
|
|
|
|
|
if cocotb.SIM_NAME:
|
|
|
|
factory = TestFactory(run_test)
|
|
factory.add_option("payload_lengths", [size_list])
|
|
factory.add_option("payload_data", [incrementing_payload])
|
|
factory.add_option(("space",
|
|
"stream_idle_inserter", "stream_backpressure_inserter",
|
|
"axi_0_idle_inserter", "axi_0_backpressure_inserter",
|
|
"axi_idle_inserter", "axi_backpressure_inserter"), [
|
|
(False, None, None, None, None, None, None),
|
|
(False, cycle_pause, None, None, None, None, None),
|
|
(False, None, cycle_pause, None, None, None, None),
|
|
(False, None, None, cycle_pause, None, None, None),
|
|
(False, None, None, None, cycle_pause, None, None),
|
|
(False, None, None, None, None, cycle_pause, None),
|
|
(False, None, None, None, None, None, cycle_pause),
|
|
(True, None, None, None, None, None, None),
|
|
(True, cycle_pause, None, None, None, None, None),
|
|
(True, None, cycle_pause, None, None, None, None),
|
|
(True, None, None, cycle_pause, None, None, None),
|
|
(True, None, None, None, cycle_pause, None, None),
|
|
(True, None, None, None, None, cycle_pause, None),
|
|
(True, None, None, None, None, None, cycle_pause),
|
|
])
|
|
factory.generate_tests()
|
|
|
|
for test in [
|
|
run_test_tuser_assert,
|
|
run_test_init_sink_pause,
|
|
run_test_overflow
|
|
]:
|
|
|
|
factory = TestFactory(test)
|
|
factory.generate_tests()
|
|
|
|
for test in [
|
|
run_test_init_sink_pause_reset,
|
|
run_test_shift_in_reset,
|
|
run_test_shift_out_reset,
|
|
]:
|
|
|
|
factory = TestFactory(test)
|
|
factory.add_option("reset_type", [TB.reset, TB.reset_source,
|
|
TB.reset_sink, TB.reset_axi_0, TB.reset_axi, TB.reset_cfg])
|
|
factory.generate_tests()
|
|
|
|
factory = TestFactory(run_stress_test)
|
|
factory.add_option(("space",
|
|
"stream_idle_inserter", "stream_backpressure_inserter",
|
|
"axi_0_idle_inserter", "axi_0_backpressure_inserter",
|
|
"axi_idle_inserter", "axi_backpressure_inserter"), [
|
|
(False, None, None, None, None, None, None),
|
|
(False, cycle_pause, None, None, None, None, None),
|
|
(False, None, cycle_pause, None, None, None, None),
|
|
(False, None, None, cycle_pause, None, None, None),
|
|
(False, None, None, None, cycle_pause, None, None),
|
|
(False, None, None, None, None, cycle_pause, None),
|
|
(False, None, None, None, None, None, cycle_pause),
|
|
(True, None, None, None, None, None, None),
|
|
(True, cycle_pause, None, None, None, None, None),
|
|
(True, None, cycle_pause, None, None, None, None),
|
|
(True, None, None, cycle_pause, None, None, None),
|
|
(True, None, None, None, cycle_pause, None, None),
|
|
(True, None, None, None, None, cycle_pause, None),
|
|
(True, None, None, None, None, None, cycle_pause),
|
|
])
|
|
factory.generate_tests()
|
|
|
|
|
|
# cocotb-test
|
|
|
|
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
|
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
|
|
|
|
|
@pytest.mark.parametrize(("axis_data_width", "axi_ch", "axi_data_width"), [
|
|
# (32, 1, 32),
|
|
# (32, 2, 32),
|
|
(512, 2, 512),
|
|
])
|
|
def test_axi_vfifo(request, axis_data_width, axi_ch, axi_data_width):
|
|
dut = "axi_vfifo"
|
|
module = os.path.splitext(os.path.basename(__file__))[0]
|
|
toplevel = dut
|
|
|
|
verilog_sources = [
|
|
os.path.join(rtl_dir, f"{dut}.v"),
|
|
os.path.join(rtl_dir, "axi_vfifo_raw.v"),
|
|
os.path.join(rtl_dir, "axi_vfifo_raw_wr.v"),
|
|
os.path.join(rtl_dir, "axi_vfifo_raw_rd.v"),
|
|
os.path.join(rtl_dir, "axi_vfifo_enc.v"),
|
|
os.path.join(rtl_dir, "axi_vfifo_dec.v"),
|
|
]
|
|
|
|
parameters = {}
|
|
|
|
parameters['AXI_CH'] = axi_ch
|
|
parameters['AXI_DATA_WIDTH'] = axi_data_width
|
|
parameters['AXI_ADDR_WIDTH'] = 16
|
|
parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8
|
|
parameters['AXI_ID_WIDTH'] = 8
|
|
parameters['AXI_MAX_BURST_LEN'] = 16
|
|
parameters['AXIS_DATA_WIDTH'] = axis_data_width
|
|
parameters['AXIS_KEEP_ENABLE'] = int(parameters['AXIS_DATA_WIDTH'] > 8)
|
|
parameters['AXIS_KEEP_WIDTH'] = parameters['AXIS_DATA_WIDTH'] // 8
|
|
parameters['AXIS_LAST_ENABLE'] = 1
|
|
parameters['AXIS_ID_ENABLE'] = 1
|
|
parameters['AXIS_ID_WIDTH'] = 8
|
|
parameters['AXIS_DEST_ENABLE'] = 1
|
|
parameters['AXIS_DEST_WIDTH'] = 8
|
|
parameters['AXIS_USER_ENABLE'] = 1
|
|
parameters['AXIS_USER_WIDTH'] = 1
|
|
parameters['LEN_WIDTH'] = parameters['AXI_ADDR_WIDTH']
|
|
parameters['MAX_SEG_WIDTH'] = 256
|
|
parameters['WRITE_FIFO_DEPTH'] = 64
|
|
parameters['WRITE_MAX_BURST_LEN'] = parameters['WRITE_FIFO_DEPTH'] // 4
|
|
parameters['READ_FIFO_DEPTH'] = 128
|
|
parameters['READ_MAX_BURST_LEN'] = parameters['WRITE_MAX_BURST_LEN']
|
|
|
|
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
|
|
|
sim_build = os.path.join(tests_dir, "sim_build",
|
|
request.node.name.replace('[', '-').replace(']', ''))
|
|
|
|
cocotb_test.simulator.run(
|
|
python_search=[tests_dir],
|
|
verilog_sources=verilog_sources,
|
|
toplevel=toplevel,
|
|
module=module,
|
|
parameters=parameters,
|
|
sim_build=sim_build,
|
|
extra_env=extra_env,
|
|
)
|