mirror of
https://github.com/alexforencich/verilog-axi.git
synced 2025-01-14 06:42:55 +08:00
303 lines
8.3 KiB
Verilog
303 lines
8.3 KiB
Verilog
/*
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Copyright (c) 2019 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Testbench for axi_dp_ram
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*/
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module test_axi_dp_ram;
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// Parameters
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parameter DATA_WIDTH = 32;
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parameter ADDR_WIDTH = 16;
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parameter STRB_WIDTH = (DATA_WIDTH/8);
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parameter ID_WIDTH = 8;
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parameter A_PIPELINE_OUTPUT = 0;
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parameter B_PIPELINE_OUTPUT = 0;
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parameter A_INTERLEAVE = 0;
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parameter B_INTERLEAVE = 1;
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// Inputs
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reg clk = 0;
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reg rst = 0;
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reg [7:0] current_test = 0;
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reg a_clk = 0;
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reg a_rst = 0;
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reg b_clk = 0;
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reg b_rst = 0;
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reg [ID_WIDTH-1:0] s_axi_a_awid = 0;
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reg [ADDR_WIDTH-1:0] s_axi_a_awaddr = 0;
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reg [7:0] s_axi_a_awlen = 0;
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reg [2:0] s_axi_a_awsize = 0;
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reg [1:0] s_axi_a_awburst = 0;
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reg s_axi_a_awlock = 0;
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reg [3:0] s_axi_a_awcache = 0;
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reg [2:0] s_axi_a_awprot = 0;
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reg s_axi_a_awvalid = 0;
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reg [DATA_WIDTH-1:0] s_axi_a_wdata = 0;
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reg [STRB_WIDTH-1:0] s_axi_a_wstrb = 0;
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reg s_axi_a_wlast = 0;
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reg s_axi_a_wvalid = 0;
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reg s_axi_a_bready = 0;
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reg [ID_WIDTH-1:0] s_axi_a_arid = 0;
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reg [ADDR_WIDTH-1:0] s_axi_a_araddr = 0;
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reg [7:0] s_axi_a_arlen = 0;
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reg [2:0] s_axi_a_arsize = 0;
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reg [1:0] s_axi_a_arburst = 0;
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reg s_axi_a_arlock = 0;
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reg [3:0] s_axi_a_arcache = 0;
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reg [2:0] s_axi_a_arprot = 0;
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reg s_axi_a_arvalid = 0;
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reg s_axi_a_rready = 0;
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reg [ID_WIDTH-1:0] s_axi_b_awid = 0;
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reg [ADDR_WIDTH-1:0] s_axi_b_awaddr = 0;
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reg [7:0] s_axi_b_awlen = 0;
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reg [2:0] s_axi_b_awsize = 0;
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reg [1:0] s_axi_b_awburst = 0;
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reg s_axi_b_awlock = 0;
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reg [3:0] s_axi_b_awcache = 0;
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reg [2:0] s_axi_b_awprot = 0;
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reg s_axi_b_awvalid = 0;
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reg [DATA_WIDTH-1:0] s_axi_b_wdata = 0;
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reg [STRB_WIDTH-1:0] s_axi_b_wstrb = 0;
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reg s_axi_b_wlast = 0;
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reg s_axi_b_wvalid = 0;
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reg s_axi_b_bready = 0;
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reg [ID_WIDTH-1:0] s_axi_b_arid = 0;
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reg [ADDR_WIDTH-1:0] s_axi_b_araddr = 0;
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reg [7:0] s_axi_b_arlen = 0;
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reg [2:0] s_axi_b_arsize = 0;
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reg [1:0] s_axi_b_arburst = 0;
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reg s_axi_b_arlock = 0;
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reg [3:0] s_axi_b_arcache = 0;
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reg [2:0] s_axi_b_arprot = 0;
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reg s_axi_b_arvalid = 0;
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reg s_axi_b_rready = 0;
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// Outputs
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wire s_axi_a_awready;
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wire s_axi_a_wready;
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wire [ID_WIDTH-1:0] s_axi_a_bid;
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wire [1:0] s_axi_a_bresp;
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wire s_axi_a_bvalid;
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wire s_axi_a_arready;
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wire [ID_WIDTH-1:0] s_axi_a_rid;
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wire [DATA_WIDTH-1:0] s_axi_a_rdata;
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wire [1:0] s_axi_a_rresp;
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wire s_axi_a_rlast;
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wire s_axi_a_rvalid;
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wire s_axi_b_awready;
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wire s_axi_b_wready;
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wire [ID_WIDTH-1:0] s_axi_b_bid;
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wire [1:0] s_axi_b_bresp;
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wire s_axi_b_bvalid;
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wire s_axi_b_arready;
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wire [ID_WIDTH-1:0] s_axi_b_rid;
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wire [DATA_WIDTH-1:0] s_axi_b_rdata;
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wire [1:0] s_axi_b_rresp;
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wire s_axi_b_rlast;
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wire s_axi_b_rvalid;
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initial begin
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// myhdl integration
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$from_myhdl(
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clk,
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rst,
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current_test,
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a_clk,
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a_rst,
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b_clk,
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b_rst,
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s_axi_a_awid,
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s_axi_a_awaddr,
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s_axi_a_awlen,
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s_axi_a_awsize,
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s_axi_a_awburst,
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s_axi_a_awlock,
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s_axi_a_awcache,
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s_axi_a_awprot,
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s_axi_a_awvalid,
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s_axi_a_wdata,
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s_axi_a_wstrb,
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s_axi_a_wlast,
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s_axi_a_wvalid,
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s_axi_a_bready,
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s_axi_a_arid,
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s_axi_a_araddr,
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s_axi_a_arlen,
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s_axi_a_arsize,
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s_axi_a_arburst,
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s_axi_a_arlock,
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s_axi_a_arcache,
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s_axi_a_arprot,
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s_axi_a_arvalid,
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s_axi_a_rready,
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s_axi_b_awid,
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s_axi_b_awaddr,
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s_axi_b_awlen,
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s_axi_b_awsize,
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s_axi_b_awburst,
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s_axi_b_awlock,
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s_axi_b_awcache,
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s_axi_b_awprot,
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s_axi_b_awvalid,
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s_axi_b_wdata,
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s_axi_b_wstrb,
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s_axi_b_wlast,
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s_axi_b_wvalid,
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s_axi_b_bready,
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s_axi_b_arid,
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s_axi_b_araddr,
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s_axi_b_arlen,
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s_axi_b_arsize,
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s_axi_b_arburst,
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s_axi_b_arlock,
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s_axi_b_arcache,
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s_axi_b_arprot,
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s_axi_b_arvalid,
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s_axi_b_rready
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);
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$to_myhdl(
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s_axi_a_awready,
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s_axi_a_wready,
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s_axi_a_bid,
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s_axi_a_bresp,
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s_axi_a_bvalid,
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s_axi_a_arready,
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s_axi_a_rid,
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s_axi_a_rdata,
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s_axi_a_rresp,
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s_axi_a_rlast,
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s_axi_a_rvalid,
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s_axi_b_awready,
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s_axi_b_wready,
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s_axi_b_bid,
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s_axi_b_bresp,
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s_axi_b_bvalid,
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s_axi_b_arready,
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s_axi_b_rid,
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s_axi_b_rdata,
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s_axi_b_rresp,
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s_axi_b_rlast,
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s_axi_b_rvalid
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);
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// dump file
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$dumpfile("test_axi_dp_ram.lxt");
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$dumpvars(0, test_axi_dp_ram);
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end
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axi_dp_ram #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.STRB_WIDTH(STRB_WIDTH),
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.ID_WIDTH(ID_WIDTH),
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.A_PIPELINE_OUTPUT(A_PIPELINE_OUTPUT),
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.B_PIPELINE_OUTPUT(B_PIPELINE_OUTPUT),
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.A_INTERLEAVE(A_INTERLEAVE),
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.B_INTERLEAVE(B_INTERLEAVE)
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)
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UUT (
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.a_clk(a_clk),
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.a_rst(a_rst),
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.b_clk(b_clk),
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.b_rst(b_rst),
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.s_axi_a_awid(s_axi_a_awid),
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.s_axi_a_awaddr(s_axi_a_awaddr),
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.s_axi_a_awlen(s_axi_a_awlen),
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.s_axi_a_awsize(s_axi_a_awsize),
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.s_axi_a_awburst(s_axi_a_awburst),
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.s_axi_a_awlock(s_axi_a_awlock),
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.s_axi_a_awcache(s_axi_a_awcache),
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.s_axi_a_awprot(s_axi_a_awprot),
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.s_axi_a_awvalid(s_axi_a_awvalid),
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.s_axi_a_awready(s_axi_a_awready),
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.s_axi_a_wdata(s_axi_a_wdata),
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.s_axi_a_wstrb(s_axi_a_wstrb),
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.s_axi_a_wlast(s_axi_a_wlast),
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.s_axi_a_wvalid(s_axi_a_wvalid),
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.s_axi_a_wready(s_axi_a_wready),
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.s_axi_a_bid(s_axi_a_bid),
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.s_axi_a_bresp(s_axi_a_bresp),
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.s_axi_a_bvalid(s_axi_a_bvalid),
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.s_axi_a_bready(s_axi_a_bready),
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.s_axi_a_arid(s_axi_a_arid),
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.s_axi_a_araddr(s_axi_a_araddr),
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.s_axi_a_arlen(s_axi_a_arlen),
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.s_axi_a_arsize(s_axi_a_arsize),
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.s_axi_a_arburst(s_axi_a_arburst),
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.s_axi_a_arlock(s_axi_a_arlock),
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.s_axi_a_arcache(s_axi_a_arcache),
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.s_axi_a_arprot(s_axi_a_arprot),
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.s_axi_a_arvalid(s_axi_a_arvalid),
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.s_axi_a_arready(s_axi_a_arready),
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.s_axi_a_rid(s_axi_a_rid),
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.s_axi_a_rdata(s_axi_a_rdata),
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.s_axi_a_rresp(s_axi_a_rresp),
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.s_axi_a_rlast(s_axi_a_rlast),
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.s_axi_a_rvalid(s_axi_a_rvalid),
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.s_axi_a_rready(s_axi_a_rready),
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.s_axi_b_awid(s_axi_b_awid),
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.s_axi_b_awaddr(s_axi_b_awaddr),
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.s_axi_b_awlen(s_axi_b_awlen),
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.s_axi_b_awsize(s_axi_b_awsize),
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.s_axi_b_awburst(s_axi_b_awburst),
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.s_axi_b_awlock(s_axi_b_awlock),
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.s_axi_b_awcache(s_axi_b_awcache),
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.s_axi_b_awprot(s_axi_b_awprot),
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.s_axi_b_awvalid(s_axi_b_awvalid),
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.s_axi_b_awready(s_axi_b_awready),
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.s_axi_b_wdata(s_axi_b_wdata),
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.s_axi_b_wstrb(s_axi_b_wstrb),
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.s_axi_b_wlast(s_axi_b_wlast),
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.s_axi_b_wvalid(s_axi_b_wvalid),
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.s_axi_b_wready(s_axi_b_wready),
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.s_axi_b_bid(s_axi_b_bid),
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.s_axi_b_bresp(s_axi_b_bresp),
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.s_axi_b_bvalid(s_axi_b_bvalid),
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.s_axi_b_bready(s_axi_b_bready),
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.s_axi_b_arid(s_axi_b_arid),
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.s_axi_b_araddr(s_axi_b_araddr),
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.s_axi_b_arlen(s_axi_b_arlen),
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.s_axi_b_arsize(s_axi_b_arsize),
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.s_axi_b_arburst(s_axi_b_arburst),
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.s_axi_b_arlock(s_axi_b_arlock),
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.s_axi_b_arcache(s_axi_b_arcache),
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.s_axi_b_arprot(s_axi_b_arprot),
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.s_axi_b_arvalid(s_axi_b_arvalid),
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.s_axi_b_arready(s_axi_b_arready),
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.s_axi_b_rid(s_axi_b_rid),
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.s_axi_b_rdata(s_axi_b_rdata),
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.s_axi_b_rresp(s_axi_b_rresp),
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.s_axi_b_rlast(s_axi_b_rlast),
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.s_axi_b_rvalid(s_axi_b_rvalid),
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.s_axi_b_rready(s_axi_b_rready)
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);
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endmodule
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