mirror of
https://github.com/alexforencich/verilog-axi.git
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252 lines
7.3 KiB
Python
Executable File
252 lines
7.3 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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import axil
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module = 'axil_ram'
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testbench = 'test_%s' % module
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("%s.v" % testbench)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
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def bench():
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# Parameters
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DATA_WIDTH = 32
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ADDR_WIDTH = 16
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STRB_WIDTH = int(DATA_WIDTH/8)
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PIPELINE_OUTPUT = 0
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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s_axil_awaddr = Signal(intbv(0)[ADDR_WIDTH:])
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s_axil_awprot = Signal(intbv(0)[3:])
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s_axil_awvalid = Signal(bool(0))
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s_axil_wdata = Signal(intbv(0)[DATA_WIDTH:])
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s_axil_wstrb = Signal(intbv(0)[STRB_WIDTH:])
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s_axil_wvalid = Signal(bool(0))
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s_axil_bready = Signal(bool(0))
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s_axil_araddr = Signal(intbv(0)[ADDR_WIDTH:])
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s_axil_arprot = Signal(intbv(0)[3:])
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s_axil_arvalid = Signal(bool(0))
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s_axil_rready = Signal(bool(0))
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# Outputs
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s_axil_awready = Signal(bool(0))
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s_axil_wready = Signal(bool(0))
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s_axil_bresp = Signal(intbv(0)[2:])
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s_axil_bvalid = Signal(bool(0))
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s_axil_arready = Signal(bool(0))
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s_axil_rdata = Signal(intbv(0)[DATA_WIDTH:])
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s_axil_rresp = Signal(intbv(0)[2:])
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s_axil_rvalid = Signal(bool(0))
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# AXI4-Lite master
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axil_master_inst = axil.AXILiteMaster()
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axil_master_pause = Signal(bool(False))
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axil_master_logic = axil_master_inst.create_logic(
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clk,
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rst,
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m_axil_awaddr=s_axil_awaddr,
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m_axil_awprot=s_axil_awprot,
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m_axil_awvalid=s_axil_awvalid,
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m_axil_awready=s_axil_awready,
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m_axil_wdata=s_axil_wdata,
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m_axil_wstrb=s_axil_wstrb,
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m_axil_wvalid=s_axil_wvalid,
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m_axil_wready=s_axil_wready,
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m_axil_bresp=s_axil_bresp,
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m_axil_bvalid=s_axil_bvalid,
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m_axil_bready=s_axil_bready,
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m_axil_araddr=s_axil_araddr,
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m_axil_arprot=s_axil_arprot,
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m_axil_arvalid=s_axil_arvalid,
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m_axil_arready=s_axil_arready,
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m_axil_rdata=s_axil_rdata,
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m_axil_rresp=s_axil_rresp,
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m_axil_rvalid=s_axil_rvalid,
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m_axil_rready=s_axil_rready,
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pause=axil_master_pause,
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name='master'
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)
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# DUT
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if os.system(build_cmd):
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raise Exception("Error running build command")
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dut = Cosimulation(
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"vvp -m myhdl %s.vvp -lxt2" % testbench,
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clk=clk,
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rst=rst,
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current_test=current_test,
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s_axil_awaddr=s_axil_awaddr,
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s_axil_awprot=s_axil_awprot,
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s_axil_awvalid=s_axil_awvalid,
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s_axil_awready=s_axil_awready,
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s_axil_wdata=s_axil_wdata,
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s_axil_wstrb=s_axil_wstrb,
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s_axil_wvalid=s_axil_wvalid,
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s_axil_wready=s_axil_wready,
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s_axil_bresp=s_axil_bresp,
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s_axil_bvalid=s_axil_bvalid,
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s_axil_bready=s_axil_bready,
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s_axil_araddr=s_axil_araddr,
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s_axil_arprot=s_axil_arprot,
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s_axil_arvalid=s_axil_arvalid,
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s_axil_arready=s_axil_arready,
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s_axil_rdata=s_axil_rdata,
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s_axil_rresp=s_axil_rresp,
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s_axil_rvalid=s_axil_rvalid,
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s_axil_rready=s_axil_rready
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)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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def wait_normal():
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while not axil_master_inst.idle():
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yield clk.posedge
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def wait_pause_master():
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while not axil_master_inst.idle():
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axil_master_pause.next = True
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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axil_master_pause.next = False
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yield clk.posedge
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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# testbench stimulus
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yield clk.posedge
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print("test 1: read and write")
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current_test.next = 1
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addr = 4
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test_data = b'\x11\x22\x33\x44'
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axil_master_inst.init_write(addr, test_data)
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yield axil_master_inst.wait()
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yield clk.posedge
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axil_master_inst.init_read(addr, len(test_data))
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yield axil_master_inst.wait()
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yield clk.posedge
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data = axil_master_inst.get_read_data()
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assert data[0] == addr
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assert data[1] == test_data
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yield delay(100)
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yield clk.posedge
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print("test 2: various reads and writes")
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current_test.next = 2
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for length in range(1,8):
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for offset in range(4,8):
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for wait in wait_normal, wait_pause_master:
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print("length %d, offset %d"% (length, offset))
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addr = 256*(16*offset+length)+offset
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test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
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axil_master_inst.init_write(addr-4, b'\xAA'*(length+8))
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yield axil_master_inst.wait()
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axil_master_inst.init_write(addr, test_data)
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yield wait()
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axil_master_inst.init_read(addr-1, length+2)
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yield axil_master_inst.wait()
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data = axil_master_inst.get_read_data()
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assert data[0] == addr-1
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assert data[1] == b'\xAA'+test_data+b'\xAA'
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for length in range(1,8):
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for offset in range(4,8):
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for wait in wait_normal, wait_pause_master:
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print("length %d, offset %d"% (length, offset))
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addr = 256*(16*offset+length)+offset
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test_data = b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]
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axil_master_inst.init_write(addr, test_data)
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yield axil_master_inst.wait()
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axil_master_inst.init_read(addr, length)
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yield wait()
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yield clk.posedge
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data = axil_master_inst.get_read_data()
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assert data[0] == addr
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assert data[1] == test_data
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yield delay(100)
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raise StopSimulation
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return instances()
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def test_bench():
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sim = Simulation(bench())
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sim.run()
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if __name__ == '__main__':
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print("Running test...")
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test_bench()
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