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FPGA/verilog-axi

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History

Alex Forencich 21dbe318b4 Add AXI lite clock domain crossing module, testbench, and timing constraints

2019-07-09 00:18:27 -07:00

..

axil_cdc.tcl

Add AXI lite clock domain crossing module, testbench, and timing constraints

2019-07-09 00:18:27 -07:00