FPGA/verilog-axi
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verilog-axi/rtl
History
Alex Forencich 1753a2e6cf Remove extraneous logic
2018-08-22 22:28:15 -07:00
..
arbiter.v
Add arbiter and priority encoder modules
2018-08-22 21:50:31 -07:00
axi_adapter_rd.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_adapter_wr.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_adapter.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_fifo_rd.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_fifo_wr.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_fifo.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_ram.v
Fix some more issues in AXI RAM module
2018-08-13 16:00:29 -07:00
axi_register_rd.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_register_wr.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axi_register.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axil_adapter_rd.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axil_adapter_wr.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axil_adapter.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axil_interconnect.v
Remove extraneous logic
2018-08-22 22:28:15 -07:00
axil_ram.v
Add AXI lite RAM module and testbench
2018-08-14 23:49:40 -07:00
axil_register_rd.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axil_register_wr.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
axil_register.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
priority_encoder.v
Add arbiter and priority encoder modules
2018-08-22 21:50:31 -07:00