mirror of
https://github.com/alexforencich/verilog-axi.git
synced 2025-01-14 06:42:55 +08:00
240 lines
12 KiB
Python
Executable File
240 lines
12 KiB
Python
Executable File
#!/usr/bin/env python
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"""
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Generates an AXI lite interconnect wrapper with the specified number of ports
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"""
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import argparse
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from jinja2 import Template
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def main():
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parser = argparse.ArgumentParser(description=__doc__.strip())
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parser.add_argument('-p', '--ports', type=int, default=[4], nargs='+', help="number of ports")
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parser.add_argument('-n', '--name', type=str, help="module name")
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parser.add_argument('-o', '--output', type=str, help="output file name")
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args = parser.parse_args()
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try:
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generate(**args.__dict__)
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except IOError as ex:
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print(ex)
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exit(1)
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def generate(ports=4, name=None, output=None):
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if type(ports) is int:
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m = n = ports
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elif len(ports) == 1:
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m = n = ports[0]
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else:
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m, n = ports
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if name is None:
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name = "axil_interconnect_wrap_{0}x{1}".format(m, n)
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if output is None:
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output = name + ".v"
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print("Generating {0}x{1} port AXI lite interconnect wrapper {2}...".format(m, n, name))
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cm = (m-1).bit_length()
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cn = (n-1).bit_length()
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t = Template(u"""/*
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4 lite {{m}}x{{n}} interconnect (wrapper)
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*/
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module {{name}} #
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(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 16,
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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parameter M_REGIONS = 1,
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{%- for p in range(n) %}
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parameter M{{'%02d'%p}}_BASE_ADDR = 0,
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parameter M{{'%02d'%p}}_ADDR_WIDTH = {M_REGIONS{32'd24}},
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parameter M{{'%02d'%p}}_CONNECT_READ = {{m}}'b{% for p in range(m) %}1{% endfor %},
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parameter M{{'%02d'%p}}_CONNECT_WRITE = {{m}}'b{% for p in range(m) %}1{% endfor %},
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parameter M{{'%02d'%p}}_SECURE = 1'b0{% if not loop.last %},{% endif %}
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{%- endfor %}
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI lite slave interfaces
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*/
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{%- for p in range(m) %}
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input wire [ADDR_WIDTH-1:0] s{{'%02d'%p}}_axil_awaddr,
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input wire [2:0] s{{'%02d'%p}}_axil_awprot,
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input wire s{{'%02d'%p}}_axil_awvalid,
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output wire s{{'%02d'%p}}_axil_awready,
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input wire [DATA_WIDTH-1:0] s{{'%02d'%p}}_axil_wdata,
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input wire [STRB_WIDTH-1:0] s{{'%02d'%p}}_axil_wstrb,
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input wire s{{'%02d'%p}}_axil_wvalid,
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output wire s{{'%02d'%p}}_axil_wready,
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output wire [1:0] s{{'%02d'%p}}_axil_bresp,
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output wire s{{'%02d'%p}}_axil_bvalid,
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input wire s{{'%02d'%p}}_axil_bready,
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input wire [ADDR_WIDTH-1:0] s{{'%02d'%p}}_axil_araddr,
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input wire [2:0] s{{'%02d'%p}}_axil_arprot,
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input wire s{{'%02d'%p}}_axil_arvalid,
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output wire s{{'%02d'%p}}_axil_arready,
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output wire [DATA_WIDTH-1:0] s{{'%02d'%p}}_axil_rdata,
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output wire [1:0] s{{'%02d'%p}}_axil_rresp,
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output wire s{{'%02d'%p}}_axil_rvalid,
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input wire s{{'%02d'%p}}_axil_rready,
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{% endfor %}
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/*
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* AXI lite master interfaces
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*/
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{%- for p in range(n) %}
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output wire [ADDR_WIDTH-1:0] m{{'%02d'%p}}_axil_awaddr,
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output wire [2:0] m{{'%02d'%p}}_axil_awprot,
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output wire m{{'%02d'%p}}_axil_awvalid,
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input wire m{{'%02d'%p}}_axil_awready,
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output wire [DATA_WIDTH-1:0] m{{'%02d'%p}}_axil_wdata,
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output wire [STRB_WIDTH-1:0] m{{'%02d'%p}}_axil_wstrb,
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output wire m{{'%02d'%p}}_axil_wvalid,
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input wire m{{'%02d'%p}}_axil_wready,
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input wire [1:0] m{{'%02d'%p}}_axil_bresp,
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input wire m{{'%02d'%p}}_axil_bvalid,
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output wire m{{'%02d'%p}}_axil_bready,
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output wire [ADDR_WIDTH-1:0] m{{'%02d'%p}}_axil_araddr,
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output wire [2:0] m{{'%02d'%p}}_axil_arprot,
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output wire m{{'%02d'%p}}_axil_arvalid,
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input wire m{{'%02d'%p}}_axil_arready,
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input wire [DATA_WIDTH-1:0] m{{'%02d'%p}}_axil_rdata,
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input wire [1:0] m{{'%02d'%p}}_axil_rresp,
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input wire m{{'%02d'%p}}_axil_rvalid,
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output wire m{{'%02d'%p}}_axil_rready{% if not loop.last %},{% endif %}
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{% endfor -%}
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);
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localparam S_COUNT = {{m}};
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localparam M_COUNT = {{n}};
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// parameter sizing helpers
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function [ADDR_WIDTH*M_REGIONS-1:0] w_a_r(input [ADDR_WIDTH*M_REGIONS-1:0] val);
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w_a_r = val;
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endfunction
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function [32*M_REGIONS-1:0] w_32_r(input [32*M_REGIONS-1:0] val);
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w_32_r = val;
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endfunction
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function [S_COUNT-1:0] w_s(input [S_COUNT-1:0] val);
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w_s = val;
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endfunction
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function w_1(input val);
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w_1 = val;
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endfunction
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axil_interconnect #(
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.S_COUNT(S_COUNT),
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.M_COUNT(M_COUNT),
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.DATA_WIDTH(DATA_WIDTH),
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.ADDR_WIDTH(ADDR_WIDTH),
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.STRB_WIDTH(STRB_WIDTH),
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.M_REGIONS(M_REGIONS),
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.M_BASE_ADDR({ {% for p in range(n-1,-1,-1) %}w_a_r(M{{'%02d'%p}}_BASE_ADDR){% if not loop.last %}, {% endif %}{% endfor %} }),
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.M_ADDR_WIDTH({ {% for p in range(n-1,-1,-1) %}w_32_r(M{{'%02d'%p}}_ADDR_WIDTH){% if not loop.last %}, {% endif %}{% endfor %} }),
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.M_CONNECT_READ({ {% for p in range(n-1,-1,-1) %}w_s(M{{'%02d'%p}}_CONNECT_READ){% if not loop.last %}, {% endif %}{% endfor %} }),
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.M_CONNECT_WRITE({ {% for p in range(n-1,-1,-1) %}w_s(M{{'%02d'%p}}_CONNECT_WRITE){% if not loop.last %}, {% endif %}{% endfor %} }),
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.M_SECURE({ {% for p in range(n-1,-1,-1) %}w_1(M{{'%02d'%p}}_SECURE){% if not loop.last %}, {% endif %}{% endfor %} })
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)
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axil_interconnect_inst (
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.clk(clk),
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.rst(rst),
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.s_axil_awaddr({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_awaddr{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_awprot({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_awprot{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_awvalid({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_awvalid{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_awready({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_awready{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_wdata({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_wdata{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_wstrb({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_wstrb{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_wvalid({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_wvalid{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_wready({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_wready{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_bresp({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_bresp{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_bvalid({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_bvalid{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_bready({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_bready{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_araddr({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_araddr{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_arprot({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_arprot{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_arvalid({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_arvalid{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_arready({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_arready{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_rdata({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_rdata{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_rresp({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_rresp{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_rvalid({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_rvalid{% if not loop.last %}, {% endif %}{% endfor %} }),
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.s_axil_rready({ {% for p in range(m-1,-1,-1) %}s{{'%02d'%p}}_axil_rready{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_awaddr({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_awaddr{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_awprot({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_awprot{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_awvalid({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_awvalid{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_awready({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_awready{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_wdata({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_wdata{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_wstrb({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_wstrb{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_wvalid({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_wvalid{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_wready({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_wready{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_bresp({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_bresp{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_bvalid({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_bvalid{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_bready({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_bready{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_araddr({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_araddr{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_arprot({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_arprot{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_arvalid({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_arvalid{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_arready({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_arready{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_rdata({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_rdata{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_rresp({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_rresp{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_rvalid({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_rvalid{% if not loop.last %}, {% endif %}{% endfor %} }),
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.m_axil_rready({ {% for p in range(n-1,-1,-1) %}m{{'%02d'%p}}_axil_rready{% if not loop.last %}, {% endif %}{% endfor %} })
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);
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endmodule
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""")
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print(f"Writing file '{output}'...")
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with open(output, 'w') as f:
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f.write(t.render(
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m=m,
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n=n,
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cm=cm,
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cn=cn,
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name=name
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))
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f.flush()
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print("Done")
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if __name__ == "__main__":
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main()
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