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verilog-axi/tb
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Alex Forencich 51caad0810 Extract port counts
2021-06-01 13:22:48 -07:00
..
axi_adapter
Update testbenches
2021-04-12 22:55:38 -07:00
axi_axil_adapter
Update testbenches
2021-04-12 22:55:38 -07:00
axi_cdma
Update testbenches
2021-04-12 22:55:38 -07:00
axi_crossbar
Extract port counts
2021-06-01 13:22:48 -07:00
axi_dma
Update testbenches
2021-04-12 22:55:38 -07:00
axi_dma_rd
Update testbenches
2021-04-12 22:55:38 -07:00
axi_dma_wr
Update testbenches
2021-04-12 22:55:38 -07:00
axi_dp_ram
Update testbenches
2021-04-12 22:55:38 -07:00
axi_fifo
Update testbenches
2021-04-12 22:55:38 -07:00
axi_interconnect
Extract port counts
2021-06-01 13:22:48 -07:00
axi_ram
Update testbenches
2021-04-12 22:55:38 -07:00
axi_register
Update testbenches
2021-04-12 22:55:38 -07:00
axil_adapter
Update testbenches
2021-04-12 22:55:38 -07:00
axil_cdc
Update testbenches
2021-04-12 22:55:38 -07:00
axil_dp_ram
Update testbenches
2021-04-12 22:55:38 -07:00
axil_interconnect
Extract port counts
2021-06-01 13:22:48 -07:00
axil_ram
Update testbenches
2021-04-12 22:55:38 -07:00
axil_register
Update testbenches
2021-04-12 22:55:38 -07:00
axi.py
Fix AXI memory model bug
2018-12-06 15:14:54 -08:00
axil.py
Don't crash when omitting read or write port connections
2018-08-16 12:50:14 -07:00
axis_ep.py
Add AXI stream endpoint module
2018-12-27 13:49:48 -08:00
Makefile
Add top-level makefile
2020-12-04 15:41:10 -08:00
test_axi_adapter_16_32.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_adapter_16_32.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_adapter_32_16.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_adapter_32_16.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_adapter_32_32.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_adapter_32_32.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_axil_adapter_16_32.py
Add AXI to AXI lite adapter modules and testbenches
2019-07-08 17:51:12 -07:00
test_axi_axil_adapter_16_32.v
Add AXI to AXI lite adapter modules and testbenches
2019-07-08 17:51:12 -07:00
test_axi_axil_adapter_32_16.py
Add AXI to AXI lite adapter modules and testbenches
2019-07-08 17:51:12 -07:00
test_axi_axil_adapter_32_16.v
Add AXI to AXI lite adapter modules and testbenches
2019-07-08 17:51:12 -07:00
test_axi_axil_adapter_32_32.py
Add AXI to AXI lite adapter modules and testbenches
2019-07-08 17:51:12 -07:00
test_axi_axil_adapter_32_32.v
Add AXI to AXI lite adapter modules and testbenches
2019-07-08 17:51:12 -07:00
test_axi_cdma_32_unaligned.py
Add AXI central DMA module and testbenches
2018-12-06 17:27:44 -08:00
test_axi_cdma_32_unaligned.v
Add AXI central DMA module and testbenches
2018-12-06 17:27:44 -08:00
test_axi_cdma_32.py
Add AXI central DMA module and testbenches
2018-12-06 17:27:44 -08:00
test_axi_cdma_32.v
Add AXI central DMA module and testbenches
2018-12-06 17:27:44 -08:00
test_axi_crossbar_4x4.py
Add AXI nonblocking crossbar interconnect module and testbench
2019-02-25 18:37:46 -08:00
test_axi_crossbar_4x4.v
Add AXI nonblocking crossbar interconnect module and testbench
2019-02-25 18:37:46 -08:00
test_axi_dma_32_32.py
Add AXI DMA module and testbench
2018-12-27 14:21:06 -08:00
test_axi_dma_32_32.v
Add AXI DMA module and testbench
2018-12-27 14:21:06 -08:00
test_axi_dma_rd_32_32_unaligned.py
Add AXI read DMA module and testbenches
2018-12-03 23:29:22 -08:00
test_axi_dma_rd_32_32_unaligned.v
Add AXI read DMA module and testbenches
2018-12-03 23:29:22 -08:00
test_axi_dma_rd_32_32.py
Add AXI read DMA module and testbenches
2018-12-03 23:29:22 -08:00
test_axi_dma_rd_32_32.v
Add AXI read DMA module and testbenches
2018-12-03 23:29:22 -08:00
test_axi_dma_wr_32_32_unaligned.py
Add AXI write DMA module and testbenches
2018-12-27 14:15:51 -08:00
test_axi_dma_wr_32_32_unaligned.v
Add AXI write DMA module and testbenches
2018-12-27 14:15:51 -08:00
test_axi_dma_wr_32_32.py
Add AXI write DMA module and testbenches
2018-12-27 14:15:51 -08:00
test_axi_dma_wr_32_32.v
Add AXI write DMA module and testbenches
2018-12-27 14:15:51 -08:00
test_axi_dp_ram.py
Add AXI RAM interface modules, AXI dual port RAM module, and testbench
2019-02-01 18:22:03 -08:00
test_axi_dp_ram.v
Add AXI RAM interface modules, AXI dual port RAM module, and testbench
2019-02-01 18:22:03 -08:00
test_axi_fifo_delay.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_fifo_delay.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_fifo.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_fifo.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_interconnect_4x4.py
Add M_REGIONS and M_SECURE parameters, add address range overlap check
2018-12-03 13:17:45 -08:00
test_axi_interconnect_4x4.v
Add M_REGIONS and M_SECURE parameters, add address range overlap check
2018-12-03 13:17:45 -08:00
test_axi_ram.py
Add optional output pipeline register to AXI RAM module
2018-11-27 01:17:31 -08:00
test_axi_ram.v
Add optional output pipeline register to AXI RAM module
2018-11-27 01:17:31 -08:00
test_axi_register.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi_register.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axi.py
Properly handle read bursts in AXI model
2018-08-13 15:12:56 -07:00
test_axil_adapter_16_32.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_adapter_16_32.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_adapter_32_16.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_adapter_32_16.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_adapter_32_32.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_adapter_32_32.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_cdc.py
Add AXI lite clock domain crossing module, testbench, and timing constraints
2019-07-09 00:18:27 -07:00
test_axil_cdc.v
Add AXI lite clock domain crossing module, testbench, and timing constraints
2019-07-09 00:18:27 -07:00
test_axil_dp_ram.py
Use correct wait
2019-02-01 17:28:22 -08:00
test_axil_dp_ram.v
Add AXI lite dual-port RAM module and testbench
2019-01-17 17:48:23 -08:00
test_axil_interconnect_4x4.py
Add M_REGIONS and M_SECURE parameters, add address range overlap check
2018-12-03 13:17:45 -08:00
test_axil_interconnect_4x4.v
Add M_REGIONS and M_SECURE parameters, add address range overlap check
2018-12-03 13:17:45 -08:00
test_axil_ram.py
Update signal names
2019-01-16 19:37:15 -08:00
test_axil_ram.v
Add optional output pipeline register to AXI lite RAM
2019-01-09 00:25:40 -08:00
test_axil_register.py
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil_register.v
Change default address width to 32
2018-08-21 22:38:32 -07:00
test_axil.py
Add MyHDL AXI4 Lite master model, RAM model, and testbench
2018-08-14 23:49:11 -07:00